Patents Examined by Joshua A Lohn
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Patent number: 8856598Abstract: A system and machine-implemented method relating to identifying anomalous events by estimating a processing time for an operation, estimating a processing time for an operation; calculating a maximum threshold time based on the estimated processing time for indicating anomalous processing of the operation, periodically determining during processing of the operation an amount of processing time used to perform the operation; and sending a notification to a user indicating an anomalous run of the operation has occurred if the determined amount of processing time exceeds the maximum threshold time.Type: GrantFiled: August 5, 2011Date of Patent: October 7, 2014Assignee: Google Inc.Inventors: Sachan Madahar, Ilie O. Grigore, Kim Nga Thi Moore, Igor Belilovets
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Patent number: 8856585Abstract: Various exemplary embodiments relate to a method and related network node including one or more of the following: detecting, by a resource allocation device, a failure of server hardware; identifying a first agent device that is configured to utilize the server hardware; and taking at least one action to effect a reconfiguration of the first agent device in response to the server hardware failure. Various embodiments additionally include one or more of the following: identifying a second agent device that is configured to utilize the server hardware; and taking at least one action to effect a reconfiguration of the second agent device in response to the server hardware failure. Various embodiments additionally include one or more of the following: receiving, by the resource allocation device from a second agent device, an indication of the failure of server hardware, wherein the second agent device is different from the first agent device.Type: GrantFiled: August 1, 2011Date of Patent: October 7, 2014Assignee: Alcatel LucentInventors: Eric J. Bauer, Randee S. Adams
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Patent number: 8856597Abstract: A validation system includes a test block that operates to apply a set of inputs to a system under test, such as a test system or an executable test algorithm, and receive from said system under test a first set of outputs produced by operation of the system under test in response to application of the set of inputs. The first set of outputs, as well as a second set of outputs reflecting output produced by operation of a reference system or executable reference algorithm in response to application of the same set of inputs, is processed to make a validation determination. A validation processing block compares the first and second sets of outputs to validate the system under test as an equivalent to the reference system.Type: GrantFiled: May 24, 2012Date of Patent: October 7, 2014Assignee: STMicroelectronics, Inc.Inventors: Steven Srebranig, Paul A. Anderson
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Patent number: 8850300Abstract: A system includes a packet generator and a packet checker. The packet generator is operable to operable to generate a packet for transmission to a destination device. The packet includes a plurality of fields, including a code field that is operable to store a code generated based on an expected modification to the packet during transmission. The packet checker is associated with the destination device and is operable to receive the packet.Type: GrantFiled: October 20, 2010Date of Patent: September 30, 2014Assignee: Altera CorporationInventors: Lambertus de Jong, James Tyson
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Patent number: 8843785Abstract: Mechanisms, in a processor chip, are provided for obtaining debug data from on-chip logic of the processor chip while the processor chip is in a secure mode of operation. The processor chip is placed into a secure mode of operation in which access to internal logic of the processor chip to control the internal logic of the processor chip, by mechanisms external to the processor chip, is disabled on a debug interface of the processor chip. A triggering condition of the processor chip is detected that is a trigger for initiated debug data collection from the on-chip logic. Debug data collection is performed from the on-chip logic to generate debug data. Data is output, by the processor chip to an external mechanism, on the debug interface based on the debug data.Type: GrantFiled: June 12, 2012Date of Patent: September 23, 2014Assignee: International Business Machines CorporationInventors: Frank Haverkamp, Heiko Michel, Joerg-Stephan Vogt
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Patent number: 8826082Abstract: An embodiment of the invention is an optical communication system including: a plurality of interface boards which transmit and receive optical signals to and from interface boards facing the plurality of interface boards; and a monitoring control device which monitors states of the plurality of interface boards. A first interface board of the plurality of interface boards includes: a replacement unit capable of monitoring the states of the plurality of interface boards on behalf of the monitoring control device and independently receiving supply of power; and a control unit configured to start the replacement unit in a case where a fault occurs in the monitoring control device and stop or halt the replacement unit in a case where there is no fault in the monitoring control device.Type: GrantFiled: June 1, 2012Date of Patent: September 2, 2014Assignee: Hitachi, Ltd.Inventors: Takuya Iwasawa, Kenta Noda
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Patent number: 8819482Abstract: A distributed storage integrity system in a dispersed storage network includes a scanning agent and a control unit. The scanning agent identifies an encoded data slice that requires rebuilding, wherein the encoded data slice is one of a plurality of encoded data slices generated from a data segment using an error encoding dispersal function. The control unit retrieves at least a number T of encoded data slices needed to reconstruct the data segment based on the error encoding dispersal function. The control unit is operable to reconstruct the data segment from at least the number T of the encoded data slices and generate a rebuilt encoded data slice from the reconstructed data segment. The scanning agent is located in a storage unit and the control unit is located in the storage unit or in a storage integrity processing unit, a dispersed storage processing unit or a dispersed storage managing unit.Type: GrantFiled: October 7, 2013Date of Patent: August 26, 2014Assignee: Cleversafe, Inc.Inventors: Greg Dhuse, Andrew Baptist, Zachary J. Mark, Jason K. Resch, Ilya Volvovski
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Patent number: 8799709Abstract: A snapshot management method includes detecting a change in a configuration of a virtual machine; recording, in a storage unit, a snapshot of a file system of the virtual machine when the change in the configuration is detected; and determining a stable operation of the virtual machine by monitoring an operation status of the virtual machine and deleting, from the storage unit, the last recorded snapshot for the virtual machine when the operation status satisfies a predetermined condition.Type: GrantFiled: February 15, 2011Date of Patent: August 5, 2014Assignee: Fujitsu LimitedInventors: Fumi Iikura, Yasuhide Matsumoto
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Patent number: 8799720Abstract: Embodiments of the invention relate to the conversion and execution of functional tests. In one embodiment, a current test step of a manual functional test is executed. The test includes a set of test steps each including at least one action and one target of the action. The test is associated with an application that includes a plurality of objects to be tested. At least two of the objects are determined to be associated with the target of the test step. A user is prompted to provide a selection of one of the at least objects for association with the target of the test step. A new test step is generated. The new test step associates the object selected by the user with the target of the current test step. The new test step is designated for automatic execution in place of the current test step for subsequent executions thereof.Type: GrantFiled: February 28, 2012Date of Patent: August 5, 2014Assignee: International Business Machines CorporationInventors: Tessa A. Lau, Jalal U. Mahmud, Pablo Pedemonte
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Patent number: 8793537Abstract: In a method for detecting memory errors occurring in a computing device, a channel number of an error memory module is obtained from a first register of a memory controller of the computing device. The method analyzes an error type to obtain a rank number of the memory module from one or more specified registers of the memory controller, and finds a serial number of a memory slot into which the memory module has been inserted. According to the serial number of the memory slot and a distribution list, the method can detect the memory slot which is carrying the memory module.Type: GrantFiled: May 17, 2012Date of Patent: July 29, 2014Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Jie-Jun Tan, Yu-Long Lin
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Patent number: 8788877Abstract: In one embodiment, a computer program product includes a computer readable storage medium having computer readable program code embodied therewith, configured for: validating a replication of copy services between a first storage system and a second storage system, removing a plurality of existing copy relationships between the first storage system and a failed storage system, creating a plurality of copy relationships between the first storage system and the second storage system, and synchronizing a plurality of data between the first storage system and the second storage system. In more embodiments, a system includes logic for performing the above functionality, and a method includes steps for performing the above functionality.Type: GrantFiled: August 3, 2011Date of Patent: July 22, 2014Assignee: International Business Machines CorporationInventors: Amy N. Blea, David R. Blea, William D. Olsen, John J. Wolfgang
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Patent number: 8775878Abstract: An information processing apparatus which make it possible to confirm an error recovery event. A device proxy server as an information processing apparatus is connected to a printer and a client PC via a network. The device proxy server receives an event message indicative of an event having occurred in a printer. The received event message is transferred to a client PC. When the event message transferred to the client PC is related to an error event indicative of an error having occurred in the printer, the device proxy server monitors whether or not the error event has been eliminated in the printer. When the error event is eliminated in the printer, the device proxy server sends an error recovery message indicative of elimination of the error event to the client PC.Type: GrantFiled: August 4, 2011Date of Patent: July 8, 2014Assignee: Canon Kabushiki KaishaInventor: Masashi Nishiyama
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Patent number: 8762793Abstract: A method begins by a processing module monitoring a reprovisioned memory device that has been reprovisioned from a legacy storage protocol to an error coding dispersed storage protocol. The method continues with the processing module determining a data migration scheme for migrating a plurality of encoded data slices stored on the reprovisioned memory device and migrating the plurality of encoded data slices from the reprovisioned memory device to one or more other memory devices in accordance with the data migration scheme when a usable memory life of the reprovisioned memory device in the error coding dispersed storage protocol has expired.Type: GrantFiled: August 5, 2011Date of Patent: June 24, 2014Assignee: Cleversafe, Inc.Inventors: Gary W. Grube, Timothy W. Markison, Jason K. Resch, Ilya Volvovski, Manish Motwani
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Patent number: 8751864Abstract: In one embodiment, the present invention provides an ability to handle an error occurring during a memory migration operation in a high availability system. In addition, a method can be used to dynamically remap a memory page stored in a non-mirrored memory region of memory to a mirrored memory region. This dynamic remapping may be responsive to a determination that the memory page has been accessed more than a threshold number of times, indicating a criticality of information on the page. Other embodiments are described and claimed.Type: GrantFiled: March 22, 2013Date of Patent: June 10, 2014Assignee: Intel CorporationInventors: Robert C. Swanson, Mahesh S. Natu, Rahul Khanna, Murugasamy K. Nachimuthu, Sarathy Jayakumar, Anil S. Keshavamurthy, Narayan Ranganathan
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Patent number: 8739010Abstract: An integrated circuit may have an array of memory elements. Each memory element may have multiple memory cells. Each memory element may have a voting circuit that receives signals from the memory cells in that memory element. The voting circuit can produce an output based on the signals. The signals stored by the memory cells of each memory element may be redundant so that the voting circuit can produce an accurate output even in the event that a radiation strike causes some of the memory cells to flip their states to erroneous values. The memory elements may be based on memory cells such as static random-access memory cells and thyristor-based cells.Type: GrantFiled: November 19, 2010Date of Patent: May 27, 2014Assignee: Altera CorporationInventor: Yanzhong Xu
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Patent number: 8726099Abstract: Disclosed is a data processing system capable of detecting a sign of abnormality in such a manner as to increase the degree of safety and availability of the system. The data processing system uses a prediction circuit that detects a sign of abnormality in accordance with a cumulative history of significant events encountered during the processing of CPUs. The prediction circuit retains latest notification timing information about periodic notification from the CPUs in association with the CPUs, acquires elapsed time from the latest notification timing at predetermined intervals, and successively retains history information corresponding to changes in the elapsed time from a target value in association with the CPUs. When the retained history information reaches a predetermined threshold value, the prediction circuit concludes that there is a sign of abnormality.Type: GrantFiled: August 4, 2011Date of Patent: May 13, 2014Assignee: Renesas Electronics CorporationInventor: Yasuhiko Saito
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Patent number: 8713358Abstract: A method begins a first rebuilder application identifying a data slice having a storage error. The method continues with the first rebuilder application or a second rebuilder application identifying a data segment based on the identified data slice. The method continues with the second rebuilder application identifying one or more other slice servers that are storing other data slices of the encoded data segment. The method continues with the second rebuilder application receiving a sufficient number of the other data slices to reconstruct the data segment and decoding them to reconstruct the data segment. The method continues with the second rebuilder application encoding the reconstructed data segment in accordance with the information dispersal algorithm to produce a new set of data slices and selecting one of them as the rebuild data slice.Type: GrantFiled: June 10, 2013Date of Patent: April 29, 2014Assignee: Cleversafe, Inc.Inventors: Vance T. Thorton, Jamie Bellanca, Dustin M. Hendrickson, Zachary J. Mark, Ilya Volvovski
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Patent number: 8707146Abstract: A method for conditionally stopping execution of a turbo decoder is proposed. The decoder has elementary decoders. Each elementary decoder performs a sequence of decoding operations and is arranged to receive an input from at least one other elementary decoder. The method determines for each specific decoding operation if the sequence of elementary decoding operations of the specific elementary decoder has substantially converged or substantially diverged. The method terminates the execution of decoding operations if a number of sequences has substantially converged or substantially diverged.Type: GrantFiled: February 5, 2009Date of Patent: April 22, 2014Assignee: Ericsson Modems SAInventors: Sébastien Charpentier, Andrea Ancora
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Patent number: 8707125Abstract: A method for transmitting encoded data, which improves a diversity effect in a communication system, including generating parity bits for an information word, generating a codeword by encoding an information word using the generated parity bits, puncturing some of the parity bits of the codeword, transmitting a frame including the information word, and generating additional parity bits for decoding the information word and transmitting the additional parity bits in one or more other frames.Type: GrantFiled: November 18, 2010Date of Patent: April 22, 2014Assignee: Samsung Electronics Co., LtdInventors: Hong-Sil Jeong, Sung-Ryul Yun, Jae-Yoel Kim, Hyun-Koo Yang, Hak-Ju Lee, Se-Ho Myung, Jin-Hee Jeong
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Patent number: 8700957Abstract: Systems and methods for remotely performing testing or scanning of boards, devices and/or systems across a network to validate code stored in the subject circuits, including validation of non-volatile storage such as Flash memory and volatile storage such as RAM, containing stable content of known patterns.Type: GrantFiled: April 24, 2012Date of Patent: April 15, 2014Assignee: Electronic Warfare Associates, Inc.Inventors: George Bernard La Fever, Iser B. Flaum