Abstract: A method begins by identifying a data slice requiring rebuilding to produce an identified data slice, wherein the identified data slice is one of a plurality of data slices that constitute a data segment and wherein each of the plurality of data slices is assigned for storage by a corresponding one of a plurality of data slice servers. The method continues by retrieving at least m number of data slices from at least m number of the plurality of data slice servers, wherein m data slices of the plurality of data slices enable reconstruction of the data segment, and wherein the at least m number of data slices does not include the identified data slice. The method continues by reconstructing the identified data slice from the at least m number of data slices to produce a rebuilt data slice. The method continues by writing the rebuilt data slice to the corresponding one of the plurality of data slice servers or to a new slice server.

Abstract: Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of protecting data using page stripes and auxiliary protection stripes. The controller stores the data in a manner such that the pages making up each page stripe include a plurality of data pages and at least one data protection page and the pages making up each auxiliary protection stripe include a plurality of data pages and an auxiliary protection page. At least a plurality of data pages are within one page stripe and one auxiliary protection stripe such that each data page is protected both by a data protection page in the page stripe and an auxiliary protection page in the auxiliary protection stripe.

Abstract: Long running computer implemented processes are dynamically adapted to improve data consistency. A range of process steps in a long running computer implemented process is specified. Additionally, each of the computer-implemented process partners that are associated with the execution of the long running process are identified within the range of specified process steps. Monitoring information is also collected with regard to at least one identified process partner. An automatic determination is made as to whether each monitored process partner is available before initiating execution of the specified range of process steps in an instance of the long running computer implemented process and a flow of the long running computer implemented process is transformed based at least in part upon the determination as to whether each monitored process partner is available.

Abstract: A distributed storage integrity system in a dispersed storage network includes a scanning agent and a control unit. The scanning agent identifies an encoded data slice that requires rebuilding, wherein the encoded data slice is one of a plurality of encoded data slices generated from a data segment using an error encoding dispersal function. The control unit retrieves at least a number T of encoded data slices needed to reconstruct the data segment based on the error encoding dispersal function. The control unit is operable to reconstruct the data segment from at least the number T of the encoded data slices and generate a rebuilt encoded data slice from the reconstructed data segment. The scanning agent is located in a storage unit and the control unit is located in the storage unit or in a storage integrity processing unit, a dispersed storage processing unit or a dispersed storage managing unit.

Abstract: A receiver apparatus comprises a LDPC decoder that can apply an accelerated belief propagation method for iteratively decoding each code block. When the number of iterations reaches a certain threshold value, the accelerated belief propagation method can adjust the initial condition used in each iteration. The initial condition is adjusted so as to enhance the likelihood of convergence in the iterative method. As a result, performance of the decoder and receiver apparatus can be improved.

Abstract: Methods and systems mitigate a soft error in an integrated circuit. A map is stored in a memory, and the map specifies a criticality class for each storage bit in the integrated circuit. A mitigative technique is associated with each criticality class. The soft error is detected in a corrupted one of the storage bits. The mitigative technique is performed that is associated with the criticality class specified in the map for the corrupted storage bit.

Abstract: A transmitting unit divides a transmit data into a plurality of code blocks, and encodes each of the plurality of code blocks to generate a transmission signal. The transmitting unit transmits the transmission signal, and a receiving unit receives the transmission signal as a reception signal. The receiving unit receives performs an iterative decoding to each of the plurality of code blocks of the reception signal. The iterative decoding is terminated to a first code block group in which an error has not been detected before a first setting iteration count. The receiving unit, when being an error in the reception signal, transmits a retransmission request feedback data which contains a NACK data and a data indicating the first code block group to the transmitting unit. First resources are assigned for each of the plurality of code blocks of the transmission signal.

Abstract: An error correction decoder (101) counts the number of times of iterative decoding executed in the process of a predetermined error correcting operation, and outputs the iterative decoding count to an averaging circuit (102). The averaging circuit (102) calculates the average value of the iterative decoding counts input from the error correction decoder (101), and outputs the calculated average value of the iterative decoding counts to a comparator (103). The comparator (103) determines whether the iterative decoding count average value is larger than a predetermined threshold value. When determining that the average value is larger than the predetermined threshold value, the comparator (103) determines that a channel switching condition is met, and outputs a channel switching signal to a channel switching circuit (405).

Abstract: A method for data storage includes performing an erasure operation on a group of analog memory cells (32). One or more of the memory cells in the group, which failed the erasure operation, are identified as erase-failed cells. A storage configuration that is used for programming the analog memory cells in the group is modified responsively to the identified erase-failed cells. Data is stored in the group of the analog memory cells using the modified storage configuration.

Abstract: Various embodiments of the present invention provide systems and methods for detecting storage medium defects. As one example, a media defect detection system is disclosed that includes a data detector circuit that applies a detection algorithm to the data input and provides a hard output and a soft output. A first circuit combines a first derivative of the hard output with a derivative of the data input to yield a first combined signal. A second circuit combines a second derivative of the hard output with a derivative of the first combined signal to yield a second combined signal. A third circuit combines a derivative of the soft output with the second combined signal and a threshold value to yield a defect signal.

Abstract: An apparatus and method for rate dematching in a communication system are provided. The apparatus includes an input sequence generator, an error calculator, and a puncture/repetition determiner. The input sequence generator calculates if current input data among data, which are input in interleaved sequence, corresponds to any nth sequence among before-interleaved sequence. The error calculator calculates an error for the current input data using the calculated sequence. The puncture/repetition determiner determines type of the current input data using the error for the current input data.

Abstract: A wireless device includes a functional unit, a wireless transceiver, an antenna and a clock. The wireless transceiver and antenna are coupled to the functional unit. The clock is coupled to the functional unit and the wireless transceiver. The clock is generates a clock signal. The wireless device is coupled wirelessly to a wireless slave device. The functional unit is configured to determine an amount of time since a last keep alive transmission with the slave device has occurred based on the clock. The functional unit determines a number of keep alive transmissions to transmit to the slave device, and appropriate transmission times for the keep alive transmissions relative to a next scheduled keep alive transmission time, based on the determined amount of time since the last keep alive transmission. The functional unit begins successive transmission of the keep alive transmissions to the slave device per the transmission times.

Abstract: A method is for decoding a block of N information items encoded with an error correction code and mutually correlated. The method includes carrying out a first decorrelation of the N information items of a block is carried out, and storing the block decorrelated. The method also includes a performing a processing for decoding a group of P information items of the block, and decorrelating at least part of the P decoded information items. The processing for decoding the group of P information items and the decorrelation are repeated with different successive groups of P information items of the block until the N information items of the block have been processed, until a decoding criterion is satisfied.

Abstract: A path monitor, a method of monitoring a path, an integrated circuit and a library of standard logic elements. In one embodiment, the path monitor includes: (1) a delay element having an input couplable to an input of a clocked flip-flop associated with a path to be monitored and configured to provide a predetermined delay and (2) a clocked exclusive OR gate having a clock input, a first input coupled to an output of the delay element, a second input couplable to the output of the clocked flip-flop and an output at which the clocked exclusive OR gate is configured to respond to a clock signal to provide an error signal only when logic levels of the first input and the second input differ.

Abstract: A network appliance for monitoring, diagnosing and documenting problems among a plurality of devices and processes (objects) coupled to a computer network utilizes periodic polling and collection of object-generated trap data to monitor the status of objects on the computer network. The status of a multitude of objects is maintained in memory utilizing virtual state machines which contain a small amount of persistent data but which are modeled after one of a plurality of finite state machines. The memory further maintains dependency data related to each object which identifies parent/child relationships with other objects at the same or different layers of the OSI network protocol model. A decision engine verifies through on-demand polling that a device is down. A root cause analysis module utilizes status and dependency data to locate the highest object in the parent/child relationship tree that is affected to determine the root cause of a problem.

Abstract: Cooperative concatenated coding techniques are provided for wireless communications between at least two users and a base station. A network system employing cooperative concatenated coding includes cooperating user devices each configured to encode and transmit at least a potion of a joint message. The joint message includes at least a potion of a first message from a first cooperating user device and at least a potion of a second message from a second cooperating user device. An embodiment includes encoding a first message from a first cooperating user, receiving a second message from a second cooperating user and decoding the second message. The methodology also includes re-encoding at least a potion of the decoded message with at least a potion of the first message to form a combined message, and then transmitting at least a potion of the combined message.

Abstract: A Flash-based memory system comprises a plurality of Flash memory devices, a Flash controller communicating independently with each Flash memory device to perform memory operations, a power circuit providing power the Flash memory devices, and a CPU configured to perform a controlled powering down procedure upon detecting a power failure. In some embodiments, the Flash-based memory system includes a backup power source having a charge storage device and charging circuitry, the CPU configured to perform one or more test procedures on the charge storage device to provide an indication of a charge storage capacity of the charge storage device. A plurality of Flash-based memory systems may be mounted on a Flash-based memory card, and multiple such Flash-based memory cards may be combined into a Flash-based memory module. A number of Flash-based memory modules may then be removably mounted in a rack-mountable housing to form unitary Flash-based memory unit.

Abstract: A transmitting system and a method of transmitting digital broadcast signal are disclosed. This invention extends a region for mobile service data in a slot. Thus, the transmitter can transmit more mobile service data. This invention has an advantage enhancing the reception performance of a broadcast signal at a reception system, and a method for processing a broadcast signal by inserting additional known data in regions C, D and E.

Abstract: One embodiment of the present invention relates to a method of reducing imprint of a memory cell. The method comprises adding an inversion condition bit operably associated with one or more memory cells storing a memory word. The inversion condition bit indicates whether the memory word represents an actual payload or an inversion of the actual payload. The inversion condition bit and memory word are selectively toggled by a control circuitry. Inversion is performed by reading the inversion condition bit and memory word and rewriting the memory word back to the one or more memory cells in an inverted or non-inverted state, depending on an inversion condition bit. The inversion condition bit is then written to the inversion status bit value. The memory address is incremented, and the inversion status data state is toggled once the address counter addresses the entire memory array. Other methods and circuits are also disclosed.

Abstract: A processor has an ALU, a load/store unit, a timer, an ECC calculator, and a plurality of ECC registers. When the load/store unit writes data in a main memory, the load/store unit writes written data and a count value of a timer in the main memory, and sets ECC status flag which indicates that an ECC about the written data is not correct in the main memory, and causes the ECC calculator to calculate the ECC about the written data after setting the ECC status flag, and writes the calculated ECC in the main memory and resets the ECC status flag after the ECC is calculated.