Abstract: A two-wire process transmitter for use in monitoring an industrial process includes HART® communication circuitry and Fieldbus communication circuitry to couple to a two-wire process control loop. A first pair of electrical terminals is provided to couple the HART® communication circuitry to the two-wire process control loop in a first configuration, and a second pair of electrical terminals is provided to couple the Fieldbus communication circuitry to the two-wire process control loop in an alternative second configuration.

Abstract: A direct memory access (DMA) first-in-first-out (FIFO) buffer includes two FIFO devices connected in parallel. An output multiplexer is controlled by a controller to pass to its output data provided by a selected one of the FIFO devices. Data is clocked into one FIFO device until it is full, after which data may be written from it. When data is written from a FIFO device, the FIFO device is emptied before data is again read into it. Using this arrangement, data can be read into one FIFO device while data is written from the other FIFO device.

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Abstract: A method and apparatus is disclosed for the automatic configuration of a communication input /output port or terminal on a communication device. The communication device comprises one or more input/output ports or terminals, one or more switching devices, some form of switch device controller, and one or more communication circuitry, configured to facilitate communication with a remotely located communication terminal. The one or more input/output ports or terminals of the communication device connect to one or more communication cables or wires configured to transfer data with the remotely located communication terminal. In one configuration the communication cables comprise two twisted pair wires as is commonly installed for telephone communication and utilized for DSL communication service. To achieve automatic configuration, the switching device is initially set in a default position connecting the communication circuitry to at least one of the communication cables.

Abstract: A device for effecting communication between a peripheral and a host computer of the present invention. The invention is particularly well-adapted for use with printers, copies and other devices not equipped with consumable resource sensing technology at the time of manufacture. In general, the inventive device is disposed within a separate housing and includes an interface for effecting signal translation and routing as necessary between the peripheral and a host computer. The device further includes first mechanisms for effecting communication between a sensor operationally coupled to the peripheral and the interface. Further included are second mechanisms for effecting communication between the interface and the host computer. Plural sensors may be operationally coupled to the peripheral. In the best mode, the sensors are E-LABELtm sensors. The interface may be implemented with a microprocessor, digital logic or simple discrete components depending on the application.

Abstract: Systems and methods to regulate real-time data capture rates to match processor-bounded data consumption operations are described. In one aspect, a computer system is connected to a data source. A first transition time is determined for the data source to change from a first mode to a second mode. A second transition time is determined for the data source to change from the second mode to the first mode. Based on the first and second transition times, the data source is set into respective ones of the first and second modes. This is performed such that real-time capture of data from the data source is regulated by the computer system to substantially match processor-bound data consumption rates of an application consuming the data.

Abstract: A disk drive is disclosed which links disk commands that access near sequential data sectors. The linked and non-linked disk commands are inserted into an input/output queue and selected for execution according to a rotational position optimization (RPO) algorithm. If an error occurs while executing a linked disk command, the disk commands are unlinked and at least one of the unlinked disk commands is executed. The residual unlinked disk commands are inserted back into the input/output queue for later execution in an order determined by the RPO algorithm.

Abstract: Method and apparatus are described that translate addresses of transactions. A first interface may receive a first address portion of a first transaction and a first address portion of a second transaction. The first address portion may be translated to a second address portion prior to receiving all portions of the first transaction. The first address portion of the second transaction may be translated to a second address portion prior to receiving all portions of the first transaction.

Abstract: Described are a storage system and a method for adapting to an incompatible disk drive that has been installed in a storage enclosure. An adapter board receives a signal from a control board that indicates a type of the control board. In response to the first signal, the adapter board determines whether the type of the control board is compatible with a disk drive that is installed in the storage enclosure. If the control board is of an incompatible type, the adapter board sends a signal to the control board that causes the control board to bypass the installed disk drive.

Abstract: A computer peripheral device learning apparatus includes a host computer, a communication path, and a computer peripheral device. The host computer includes a peripheral device driver configured to generate an output job. The computer peripheral device communicates with the host computer via the communication path. The computer peripheral device is configured to generate an output job in a first output job format. Furthermore, the computer peripheral device is operative to receive instructions from an external source on how to generate an output job in a second output job format. A method is also provided.

Abstract: A method, system, and apparatus for preventing input/output (I/O) adapters used by an operating system (OS) image, in a logically partitioned data processing system, from fetching or corrupting data from a memory location allocated to another OS image within the data processing system is provided. A hypervisor prevents transmission of data between an input/output adapter in one of the logical partitions and memory locations assigned to other logical partitions during a direct memory access (DMA) operation by assigning each of the input/output adapters a range of I/O bus DMA addresses. The I/O adapters (IOAs) are connected to PCI host bridges via terminal bridges. A single terminal bridge may support multiple IOAs, in which case every terminal bridge has a plurality of sets of range registers, each associated with a respective one of the IOAs to which it is connected. An arbiter is provided which selects one of the input/output adapters to use the PCI bus.

Abstract: A method and apparatus for performing serial communication between a host apparatus and a plurality of peripheral devices, such as an optional sheet bank, using an I2C bus. The host apparatus includes a processor connected to the I2C bus. A respective logic circuit is provided in each of the plurality of peripheral devices. The logic circuits are configured to be serially-connectable and communicable with the host apparatus through the I2C bus and to output a unique logic value based on a number of the peripheral devices serially connected to the host apparatus. Further, the host apparatus assigns an identification to each of the plurality of peripheral devices using the unique logic value.

Abstract: A method and system for accessing a shared memory in a deterministic schedule. In one embodiment, a system comprises a plurality of processing elements and a system I/O controller where each processing element and system I/O controller comprises a DMA controller. The system further comprises a shared memory coupled to each of the plurality of processing elements where the shared memory comprises a master controller. The master controller may then issue tokens to DMA controllers to grant the right for the associated processing elements and system I/O controller to access the shared memory at deterministic points in time. Each token issued by the master controller grants access to the shared memory for a particular duration of time at a unique deterministic point in time. A processing element or system I/O controller may access the shared memory upon the associated DMA controller relinquishing to the master controller the token that grants the right to access the shared memory at that particular time.

Abstract: A first-in, first-out (FIFO) memory system (10) includes first and second FIFOs (A and B). First and second multiplexers (12, 14) each have two input terminals for receiving data. An output terminal of the first multiplexer (12) is coupled to the first FIFO (A) and an output terminal of the second multiplexer (14) is coupled to the second FIFO (B). In response to the data being one data type, write control logic (90, 95, 100) is used to cause the data to be alternately written to the first and second FIFOs (A, B). In response to the data being a second data type, write control logic (90, 95, 100) is used to cause the data to be simultaneously written to the first and second FIFOs (A, B).

Abstract: A serial-data transfer system can concurrently transfer the same data from a master device to an optional number of slave devices. In the a serial-data transfer system, at least one master device and a plurality of slave devices are connected via a serial-data line for transferring data and a serial-clock line for transferring clock signals controlling the data transfer. In a normal mode, address information corresponding to an inherent address of each of the slave devices is transmitted from the master device to each of the slave devices, and interactive data communication is performed between the master device and the slave devices each having an inherent address matching the address information. In a local mode, address information corresponding to a common address is transmitted from the master device to a plurality of the slave devices which is intended to be specified, thereby specifying the plurality of the slave devices and concurrently transmitting the same data to the plurality of the slave devices.

Abstract: Provided is a method, system, and program for maintaining status information on data transmitted to an output device. Data is transmitted to an Input/Output (I/O) device. The I/O device stores the transmitted data in a computer readable medium memory. A determination is made as to whether a fixed amount of data exceeding a threshold was transmitted. An indication is made that transmitted data equivalent to the fixed amount was successfully outputted from the computer readable medium after determining that the fixed amount of data exceeding the threshold was transmitted.

Abstract: Communications between an adapter card and a host computer system are established by embedding a server program within a BIOS extension stored in a memory on the adapter card. The BIOS extension is loaded into the host memory during normal execution of the host system BIOS for execution by the host processor. When executed by the host processor, the BIOS extension code copies the server program embedded within it to a new location in host memory, and then hooks the new location of the server program to a pre-selected interrupt of the host computer system to cause the host processor to initiate execution of the server program on the host computer system upon a subsequent occurrence of that interrupt. When executed on the host computer, the server program then establishes two-way communications with a client program executing on the adapter card.

Abstract: A process of handling packet data in a packet buffer is disclosed. Free pointers are stored in a plurality of free pointer queues, with each of the plurality free pointer queues in a form of a linked list and the free pointers are retrieved from each of the plurality of free pointer queues and storing in a prefetch memory to provide a throughput of one free pointer per clock cycle. When an initial portion of a data packet is received, two free pointers are retrieved from the prefetch memory. One of the two free pointers is stored in a start pointer register connoting a start of the data packet and one free pointer is supplied for data elements of the data packet. One free pointer per middle data element is supplied, while no new pointer is needed for the end of packet data element.

Abstract: The present invention is primarily directed to rail car communication system and in particular communication system used to transfer data and voice communications from one car to another. The present invention has particular applicability for use in subway cars. A communication system using an E1 protocol is provided with an interface device which translates data received from a hardware device having, inter alia, a microprocessor and a universal asynchronous receiver transmitter (UART) used for serial communications such as COM 1-4. The asynchronous UART data is interfaced with the E1 channel. UART data transfers are usually done on a byte (8 bits) by byte basis but the present invention uses E1 timing and bit by bit communications. Additionally, data is normally sent at the data rate of the E1 channel not some other unrelated speed such as those used by a UART during serial communications. Also, the data is usually sent synchronously, like the E1 channel, not asynchronously, as with a UART.

Abstract: An arrangement is disclosed for use in connection with a host computer connected to a mass storage subsystem, the mass storage subsystem storing information for use in connection with processing of at least one program by the host computer. The arrangement comprises a program input/output interface, a mass storage subsystem interface and a file system control. The program input/output interface is configured to receive program input/output read and write requests from a program, each program input/output read and write request initiating an input/output operation in connection with information stored on a mass storage subsystem. The mass storage subsystem interface is configured to facilitate communications with the mass storage subsystem, including transferring a storage subsystem input/output read and write request thereto and receiving information therefrom.