Patents Examined by Jue Zhang
  • Patent number: 11967890
    Abstract: A frequency converter includes: at least one bridge arm, wherein a shunt resistor is arranged in the bridge arm; an evaluation device having an input connection, the evaluation device being designed to evaluate a measurement signal which is present at the input connection and which is dependent on a voltage drop across the shunt resistor, in order to determine a measured variable; and a voltage peak suppression device, which is designed to short-circuit the input connection of the evaluation device when a voltage peak occurs at the shunt resistor.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: April 23, 2024
    Assignee: Lenze SE
    Inventors: Robin Stahel, Andreas Burgermeister
  • Patent number: 11967900
    Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator including first and second inputs. The first input is configured to receive, during a first phase, a first voltage ramp and, during a second phase, a set point voltage. The second input is configured to receive, during the first phase, the set point voltage and, during the second phase, a second voltage ramp.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: April 23, 2024
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Sebastien Ortet, Olivier Lauzier
  • Patent number: 11962249
    Abstract: According to some embodiments, an apparatus comprises a multi-level power converter configured to convert an input voltage to an output voltage, wherein the multi-level power converter comprises one or more switching groups, wherein a switching group of the one or more switching groups comprises a pair of switches and a flying capacitor, and a controller configured to determine a duty reference for the switching group, determine a duty correction factor for the switching group based upon a flying capacitor voltage error of the flying capacitor, determine a sign correction signal based on a flying capacitor ripple voltage, and determine a duty command for activating the pair of switches based on the duty reference, the duty correction factor, and the sign correction signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: April 16, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Eslam Abdelhamid, Juan Sanchez
  • Patent number: 11956929
    Abstract: A server device includes a casing, an electronic assembly, a cover, and a heat dissipation device. The electronic assembly includes a circuit board and at least one heat source. The circuit board is disposed on the casing, and the heat source is disposed on the circuit board. The cover is removably disposed on the casing. The heat dissipation device includes at least one air cooling heat exchanger and at least one liquid cooling heat exchanger. The air cooling heat exchanger is fixed on and thermally coupled with the heat source. The liquid cooling heat exchanger is fixed on the cover and thermally coupled with the air cooling heat exchanger.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: April 9, 2024
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventors: Chun-Ming Chang, Tai-Jung Sung
  • Patent number: 11949325
    Abstract: A power conversion device according to an embodiment may include: an output circuit configured to perform a power conversion operation of converting input power into an output power and outputting the output power; and a microcomputer configured to control the power conversion operation by the output circuit with power supplied from an internal power source of the output circuit, wherein the microcomputer outputs a status signal notifying whether the microcomputer is in a power shutdown permit period or a power shutdown inhibit period, and the output circuit includes a power supply stop circuit configured, when receiving the operation stop signal that instructs to stop the power conversion operation, to stop the power supply from the internal power source to the microcomputer on a condition where the status signal indicates that the microcomputer is in the power shutdown permit period.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: April 2, 2024
    Assignee: SANKEN ELECTRIC CO., LTD.
    Inventors: Junichi Takada, Toshihiro Nakano
  • Patent number: 11949348
    Abstract: A multi-pulse line-interphase transformer converter includes an electric part that includes magnetic components configured to be connected to a three-phase AC grid, and an electric part that includes a multi-phase voltage system configured to be connected to a common DC capacitor. The electric part splits each AC grid phase n times into two phases, resulting in a plurality of intermediate phases at an internal interface, each intermediate phase corresponding to a pulse of the multi-pulse line-interphase transformer converter. The intermediate phases are connected to the multi-phase voltage system. The multi-phase voltage system comprises bridges with actively controlled switches. The bridges are connected in parallel to the common DC capacitor.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: April 2, 2024
    Assignee: ABB E-mobility B.V.
    Inventors: Uwe Drofenik, Francisco Canales, Daniel Rothmund
  • Patent number: 11949318
    Abstract: An air chamber serving as a breather chamber and a breather hole that communicates the outside of a case and the air chamber can be easily molded, and breather hole is provided so as to have a degree of freedom in an installation position and volume, so that oil does not easily blow out from case in which rotary electric machine is housed. Case housing rotary electric machine has an inner and outer case portion. Inner case portion has a first coupling portion. Outer case portion has a second coupling portion. The first and second coupling portions are fixed to each other. An air chamber communicated with an inside of inner case portion is formed between outer surface of inner case portion and inner surface of outer case portion. A breather hole that communicates air chamber and an outside of case is formed in outer case portion.
    Type: Grant
    Filed: December 25, 2019
    Date of Patent: April 2, 2024
    Assignee: AISIN CORPORATION
    Inventors: Takeshi Torii, Takuro Iwase, So Shiraiwa
  • Patent number: 11940824
    Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: March 26, 2024
    Assignee: Intel Corporation
    Inventors: Xiaosen Liu, Harish Krishnamurthy, Krishnan Ravichandran, Vivek De, Scott Chiu, Claudia Patricia Barrera Gonzalez, Jing Han, Rajasekhara Madhusudan Narayana Bhatla
  • Patent number: 11940828
    Abstract: A voltage tracking circuit is provided. The voltage tracking circuit includes first and second P-type transistors and a control circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The gate and the drain of the second P-type transistor are respectively coupled to the first voltage terminal and a second voltage terminal. The control circuit is coupled to the first and second voltage terminals and generates a control voltage according to the first voltage and the second voltage. The sources of the first and second P-type transistors are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal. In response to the second voltage being higher than the first voltage, the control circuit generates the control signal to turn off the first P-type transistor.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: March 26, 2024
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shao-Chang Huang, Yeh-Ning Jou, Ching-Ho Li, Kai-Chieh Hsu, Chun-Chih Chen, Chien-Wei Wang, Gong-Kai Lin, Li-Fan Chen
  • Patent number: 11936244
    Abstract: A rotor includes a rotor core. The rotor core has an outer shape including a first arc portion provided so as to intersect a d-axis, a straight line portion provided so as to intersect a q-axis, and a curved portion that connects the first arc portion and the straight line portion. The first arc portion has an arc shape centered on an axial center of the rotor core. The curved portion includes an arc-shaped second arc portion that bulges outward in a radial direction of the rotor core. The radius of curvature of the second arc portion being smaller than a radius of curvature of the first arc portion.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: March 19, 2024
    Assignee: Daikin Industries, Ltd.
    Inventors: Kiyotaka Nishijima, Akinobu Ishizaki, Hisato Sumitomo, Takanori Hori
  • Patent number: 11929689
    Abstract: A power conversion device includes: a dead time application unit which applies a dead time to only one of a pair of pulse signals; a current polarity detection unit which detects a polarity of an output current; and a gate signal selection unit which, if the polarity of the output current is positive, selects the one pulse signal, to which the dead time has been applied, as a gate signal for a positive arm and selects the other pulse signal as a gate signal for a negative arm, and, if the polarity of the output current is negative, selects the one pulse signal, to which the dead time has been applied, as the gate signal for the negative arm and selects the other pulse signal as the gate signal for the positive arm.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: March 12, 2024
    Assignee: TOSHIBA MITSUBISHI-ELECTRIC INDUSTRIAL SYSTEMS CORPORATION
    Inventors: Ryoji Tsuruta, Hiroshi Masunaga, Tomohiro Tanaka
  • Patent number: 11929672
    Abstract: A power converter and a corresponding method of converting power are presented. The power converter includes a ground port, an input port for receiving an input voltage and an output port for providing an output voltage; an inductor; a flying capacitor; a network of switches; and a driver to drive the network of switches with a sequence of states during a drive period. The sequence of states includes a first state and a second state. In the first state one of the input port and the output port is coupled to the ground port via a first path comprising the inductor. In the second state the remaining state among the input port and the output port is coupled to the ground port via a second path and a third path, the second path comprising the flying capacitor and bypassing the inductor, and the third path comprising the inductor.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: March 12, 2024
    Assignee: Renesas Design (UK) Limited
    Inventor: Holger Petersen
  • Patent number: 11923769
    Abstract: The control system includes a PFC circuit and a sampling control circuit, and the PFC circuit includes an inductor, a first power supply drive circuit, and a first bridge arm and a second bridge arm that are connected in parallel, and a first bridge arm midpoint is a serial connection point between a first upper bridge arm and a first lower bridge arm of the first bridge arm. The sampling control circuit is configured to control, based on voltages of two ends of an alternating current power supply, the first lower bridge arm to be turned on, so that the first power supply drive circuit starts charging. The sampling control circuit is further configured to: when charging duration of the first power supply drive circuit reaches first target duration, control the first lower bridge arm to be turned off, so that the first power supply drive circuit completes charging.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: March 5, 2024
    Assignee: HUAWEI DIGITAL POWER TECHNOLOGIES CO., LTD.
    Inventors: Ken Chin, Shanglin Mo, Yuanjun Liu
  • Patent number: 11921533
    Abstract: Example implementations include a bandgap voltage device with a first current source operatively coupled to a bandgap input node and a bandgap output node and operable to output a first proportional-to-absolute-temperature (PTAT) current, a current mirror including a first bandgap transistor and a second bandgap transistor, and operatively coupled to the bandgap output node, and a second current source operatively coupled to the current mirror and operable to output a second PTAT current.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: March 5, 2024
    Assignee: Renesas Electronics America Inc.
    Inventor: Anurag Kaplish
  • Patent number: 11914410
    Abstract: Described embodiments include a circuit for controlling a voltage drop. The circuit includes a resistor coupled between an output voltage terminal and a reference voltage terminal. First, second and third switches each have respective first, second and third switch terminals. The respective second switch terminals are connected together and are coupled to the output voltage terminal. The respective third switch terminals are connected together and are coupled to the reference voltage terminal. A first transistor is coupled between a supply voltage terminal and the first switch. A second transistor is coupled between the supply voltage terminal and the second switch. A third transistor is coupled between the supply voltage terminal and the third switch. Control terminals of the first, second and third transistors are coupled to a gate control terminal.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Rajat Chauhan
  • Patent number: 11916512
    Abstract: An embodiment provides a DC-DC converter for sensing a grounded state and a method for controlling same in a photovoltaic energy storage system. Specifically, the converter can sense a grounded state on the basis of the magnitude of voltage applied to a resistor and provide a notification.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: February 27, 2024
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Sang Gyu Choi, Jae Geun Lee, Jeong Heum Lee
  • Patent number: 11914412
    Abstract: In described examples, a circuit includes a first current mirror circuit. The first current mirror circuit is coupled to a power input terminal. A first stage is coupled to the first current mirror circuit, and a second stage is coupled to the first stage and to the first current mirror circuit. An amplifier is coupled to the first and second stages. The amplifier has first and second input terminals. The first input terminal is coupled to the first stage, and the second input terminal is coupled to the second stage. A second current mirror circuit is coupled to the first stage, the second stage and the amplifier.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sanjeev Praphulla Chandra Nyshadham, Subrato Roy
  • Patent number: 11916438
    Abstract: A magnetization ring is disposed between a rotor and a core portion surrounding the rotor, the rotor having permanent magnets and inter-pole portions which are arranged in a circumferential direction about an axis. The magnetization ring has a magnetic portion facing the center of the permanent magnet in the circumferential direction, and a nonmagnetic portion facing the inter-pole portion of the rotor.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: February 27, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takanori Watanabe, Atsushi Matsuoka, Atsushi Ishikawa
  • Patent number: 11906999
    Abstract: Described embodiments include a circuit for dampening overshoot in a voltage regulator. The circuit includes a first and second offset voltage circuits, each having an input coupled to an input voltage terminal. A first comparator has a first comparator input coupled to the first offset output, and a second comparator input coupled to a reference voltage terminal. A second comparator has a third comparator input coupled to an output of the second offset circuit, and a fourth comparator input coupled to a voltage regulator output. An OR gate has first and second logic inputs and a logic output. The first and second logic inputs are coupled to the outputs of the first and second comparators, respectively. A turn-off circuit has a turn-off input coupled to the logic output, and is configured to provide a turn-off signal at a turn-off output to stop current flow from the voltage regulator output.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: February 20, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Saurabh Rai, Venkateswarlu Ramaswamy Tiruvamattur, Ramakrishna Ankamreddi
  • Patent number: 11906995
    Abstract: A voltage regulator coupled between a first node and second node includes a first (full-power) regulator circuit and a second (low-power) regulator circuit. In a first mode: the first regulator circuit is activated (with the second regulator circuit inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is kept de-activated when the voltage at the first node is a ground voltage. In a second mode: the first regulator circuitry in is active (with the second regulator circuitry inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is inactive when the voltage at the first node is a ground voltage. In a third mode: the second regulator circuitry is active (with the first regulator circuitry inactive) irrespective of the voltage at the first node being at the battery voltage or the ground voltage.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: February 20, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Daniele Mangano, Francesco Clerici, Pasquale Butta'