Patents Examined by Julia Slutsker
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Patent number: 11978827Abstract: An optical device includes a multilayered GaAs structure including a plurality of sublayers and an optical structure layer on the multilayered GaAs structure, the optical structure layer including a Group III-V compound semiconductor material. The optical structure layer may be, for example, a light-emitting layer having a multi-quantum well structure.Type: GrantFiled: October 28, 2022Date of Patent: May 7, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Changyoung Park, Sanghun Lee
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Patent number: 11978764Abstract: A capacitor structure includes a first electrode, a second electrode, a third electrode, a first dielectric layer and a second dielectric layer. The second electrode is disposed over the first electrode. The third electrode is disposed over the second electrode. The first dielectric layer is disposed between the first electrode and the second electrode. The second dielectric layer is disposed between the second electrode and the third electrode. The third electrode contacts the first electrode. A semiconductor structure thereof and a method for forming the same are also provided.Type: GrantFiled: June 10, 2022Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventor: Chih-Kuang Kao
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Patent number: 11980036Abstract: A semiconductor structure includes a substrate, an interconnection structure disposed over the substrate and a first memory cell. The first memory cell is disposed over the substrate and embedded in dielectric layers of the interconnection structure. The first memory cell includes a first transistor and a first data storage structure. The first transistor is disposed on a first base dielectric layer and embedded in a first dielectric layer. The first data storage structure is embedded in a second dielectric layer and electrically connected to the first transistor. The first data storage structure includes a first electrode, a second electrode and a storage layer sandwiched between the first electrode and the second electrode.Type: GrantFiled: July 26, 2022Date of Patent: May 7, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-I Wu, Yu-Ming Lin, Han-Jong Chia
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Patent number: 11978788Abstract: The present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on BOTH sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the “B-TRAN” type. In one advantageous group of embodiments (but not all), the breakdown initiation regions are defined by dopant introduction through the bottom of trench portions which lie within the emitter/collector region. In one group of embodiments (but not all), these can advantageously be separated trench portions which are not continuous with the trench(es) surrounding the emitter/collector region(s).Type: GrantFiled: May 24, 2023Date of Patent: May 7, 2024Assignee: IDEAL POWER INC.Inventors: Richard A. Blanchard, William C. Alexander
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Patent number: 11978658Abstract: A method for manufacturing a polysilicon SOI substrate including a cavity. The method includes: providing a silicon substrate including a sacrificial layer thereon; producing a first polysilicon layer on the sacrificial layer; depositing a structuring layer on the first polysilicon layer; introducing trenches through the structuring layer, the first polysilicon layer, and the sacrificial layer up to the silicon substrate; producing a cavity in the silicon substrate by etching, an etching medium being conducted thereto through the trenches; producing a second polysilicon layer on the first polysilicon layer, the trenches being thereby closed. A micromechanical device is also described.Type: GrantFiled: November 22, 2021Date of Patent: May 7, 2024Assignee: ROBERT BOSCH GMBHInventors: Jochen Reinmuth, Peter Schmollngruber
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Patent number: 11972942Abstract: A method of forming an integrated circuit, including first, positioning a semiconductor wafer in a processing chamber; second, exposing portions of the semiconductor wafer, including introducing a first amount of hydrogen into the processing chamber and introducing a first amount of oxygen into the processing chamber; and, third, introducing at least one of a second amount of hydrogen or a second amount of oxygen into the processing chamber, the second amount of hydrogen greater than zero and less than the first amount of hydrogen and the second amount of oxygen greater than zero and less than the first amount of oxygen.Type: GrantFiled: September 23, 2021Date of Patent: April 30, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mona M. Eissa, Corinne Ann Gagnet, Christopher Scott Whitesell, Pushpa Mahalingam
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Patent number: 11968835Abstract: A vertical type semiconductor device includes a substrate that has a plurality of trenches, a support pattern that fills the plurality of trenches and protrudes from a top surface of the substrate, a semiconductor layer disposed on the substrate that fills a space between the support patterns, a stacked structure disposed on the support pattern and the semiconductor layer that includes a plurality of insulation layers and a plurality of first conducive patterns that are alternately and repeatedly stacked, and a plurality of channel structures that penetrate through the structure and the semiconductor layer and that extend into the support pattern. Each channel structure includes a channel layer. At least a portion of the channel layer makes contact with the semiconductor layer.Type: GrantFiled: March 14, 2022Date of Patent: April 23, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-Taek Jung, Joong-Shik Shin, Byung-Kwan You
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Patent number: 11955495Abstract: The present disclosure provides an image sensing module including a main board and an image sensor. The main board has a first surface and a second surface opposite to each other. The image sensor is disposed on the first surface of the main board and includes a plurality of isolation structures and a photoelectric conversion element between the plurality of isolation structures. A first angle is provided between a light incident surface of the photoelectric conversion element and the first surface of the main board, and a second angle is provided between a light beam incident to the light incident surface of the photoelectric conversion element and a normal vector of the light incident surface. The second angle is about equal to the Brewster angle at the interface of the light beam incident to the light incident surface.Type: GrantFiled: November 21, 2022Date of Patent: April 9, 2024Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Wen-Hsien Chen
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Patent number: 11942546Abstract: A method includes forming an interfacial layer over a substrate; forming a quasi-antiferroelectric (QAFE) layer over the interfacial layer, in which forming the QAFE layer comprises performing an atomic layer deposition (ALD) cycle, and the ALD cycle includes performing a first sub-cycle for X time(s), in which the first sub-cycle comprises providing a Zr-containing precursor; performing a second sub-cycle for Y time(s), in which the second sub-cycle comprises providing a Hf-containing precursor; and performing a third sub-cycle for Z time(s), in which the third sub-cycle comprises providing a Zr-containing precursor, and in which X+Z is at least three times Y; and forming a gate electrode over the QAFE layer.Type: GrantFiled: December 3, 2020Date of Patent: March 26, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITYInventors: Kuan-Ting Chen, Shu-Tong Chang, Min-Hung Lee
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Patent number: 11923244Abstract: Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and to processes for forming such semiconductor structures and interconnects. In an embodiment, a process for fabricating a semiconductor structure is provided. The process includes performing a degas operation on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer, wherein the liner layer comprises Ti, Ta, TaN, or combinations thereof, and a resistivity of the metal layer is about 30 ??·cm or less.Type: GrantFiled: March 5, 2021Date of Patent: March 5, 2024Assignee: Applied Materials, Inc.Inventors: He Ren, Hao Jiang, Shi You, Mehul B. Naik
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Patent number: 11923324Abstract: A semiconductor memory device includes a substrate, a memory cell array separated from the substrate, and a plurality of first bonding pad electrodes away from the memory cell array. The substrate includes a plurality of first and second regions arranged alternately. The memory cell array includes a plurality of conductive layers extending across the plurality of first and second regions, a plurality of semiconductor layers disposed in the plurality of first regions, and a plurality of first contacts disposed in the plurality of second regions. When a distance between a center position of the first bonding pad electrode and a center position of the first contact closest to the first bonding pad electrode is defined as a first distance, a difference between a largest first distance and a smallest first distance among a plurality of first distances is 400 nm or less.Type: GrantFiled: March 3, 2021Date of Patent: March 5, 2024Assignee: Kioxia CorporationInventor: Masayuki Akou
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Patent number: 11923456Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.Type: GrantFiled: April 18, 2022Date of Patent: March 5, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Gil Yang, Beom-Jin Park, Seung-Min Song, Geum-Jong Bae, Dong-Il Bae
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Patent number: 11916099Abstract: A semiconductor device is provided. The semiconductor device includes: a first conductive electrode; a first dielectric stack structure provided on the first conductive electrode; a second conductive electrode provided on the first dielectric stack structure; a second dielectric stack structure provided on the second conductive electrode; and a third conductive electrode provided on the first dielectric stack structure, wherein each of the first dielectric stack structure and the second dielectric stack structure include a first dielectric layer comprising a first material; a second ferroelectric dielectric layer comprising a second material and provided on the first dielectric layer, and a third dielectric layer comprising a third material and provided on the second ferroelectric dielectric layer.Type: GrantFiled: June 8, 2021Date of Patent: February 27, 2024Assignee: International Business Machines CorporationInventors: Takashi Ando, Reinaldo Vega, David Wolpert, Cheng Chi, Praneet Adusumilli
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Patent number: 11894240Abstract: A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of a semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.Type: GrantFiled: February 25, 2021Date of Patent: February 6, 2024Assignee: TOKYO ELECTRON LIMITEDInventors: David Hurley, Ioan Domsa, Ian Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson, Gerrit J. Leusink, Robert Clark, Dina Triyoso
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Patent number: 11895883Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.Type: GrantFiled: October 28, 2021Date of Patent: February 6, 2024Assignee: Apple Inc.Inventors: Cheng-Ho Yu, Chin-Wei Lin, Shyuan Yang, Ting-Kuo Chang, Tsung-Ting Tsai, Warren S. Rieutort-Louis, Shih-Chang Chang, Yu Cheng Chen, John Z. Zhong
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Patent number: 11887845Abstract: A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×1017 atoms/cm3 or more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.Type: GrantFiled: September 29, 2021Date of Patent: January 30, 2024Assignees: GLOBALWAFERS JAPAN CO., LTD., TOHOKU UNIVERSITYInventors: Kazutaka Kamijo, Etsuo Fukuda, Takashi Ishikawa, Koji Izunome, Moriya Miyashita, Takao Sakamoto, Tetsuo Endoh
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Patent number: 11886120Abstract: Embodiments disclosed herein include methods of depositing a metal oxo photoresist using dry deposition processes. In an embodiment, the method comprises forming a first metal oxo film on the substrate with a first vapor phase process including a first metal precursor vapor and a first oxidant vapor, and forming a second metal oxo film over the first metal oxo film with a second vapor phase process including a second metal precursor vapor and a second oxidant vapor.Type: GrantFiled: June 23, 2021Date of Patent: January 30, 2024Assignee: Applied Materials, Inc.Inventors: Lakmal Charidu Kalutarage, Mark Joseph Saly, Bhaskar Jyoti Bhuyan, Thomas Joseph Knisley, Kelvin Chan, Regina Germanie Freed, David Michael Thompson, Susmit Singha Roy, Madhur Sachan
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Patent number: 11881401Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.Type: GrantFiled: May 17, 2021Date of Patent: January 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Chin Chang, Li-Te Lin, Ru-Gun Liu, Wei-Liang Lin, Pinyen Lin, Yu-Tien Shen, Ya-Wen Yeh
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Patent number: 11875992Abstract: Semiconductor devices are provided. A semiconductor device includes a first portion of a lower electrode structure on a substrate. The semiconductor device includes a first support pattern being in contact with a first portion of a sidewall of the first portion of the lower electrode structure. The semiconductor device includes a second portion of the lower electrode structure on a second portion of the sidewall of the first portion of the lower electrode structure. The semiconductor device includes an upper electrode on the second portion of the lower electrode structure and on the first support pattern. Moreover, the semiconductor device includes a dielectric layer between the upper electrode and the second portion of the lower electrode structure.Type: GrantFiled: June 28, 2022Date of Patent: January 16, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Suk Lee, Jungoo Kang, Gihee Cho, Sanghyuck Ahn
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Patent number: 11876122Abstract: A method of forming a semiconductor device. A substrate having a fin structure is provided. A dummy gate is formed on the fin structure. A polymer block is formed adjacent to a corner between the dummy gate and the fin structure. The polymer block is subjected to a nitrogen plasma treatment, thereby forming a nitridation layer in proximity to a sidewall of the dummy gate under the polymer block. After subjecting the polymer block to the nitrogen plasma treatment, a seal layer is formed on the sidewall of the dummy gate and on the polymer block. An epitaxial layer is then grown on a source/drain region of the fin structure. The dummy gate is then replaced with a metal gate.Type: GrantFiled: November 27, 2022Date of Patent: January 16, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Wei Chang, Chia-Ming Kuo, Po-Jen Chuang, Fu-Jung Chuang, Shao-Wei Wang, Yu-Ren Wang, Chia-Yuan Chang