Abstract: A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate defined with a plurality of cell areas and a plurality of coupling areas in a first direction; a hard mask pattern disposed on the electrode structure, and having a plurality of opening holes in the coupling areas; and a plurality of contact holes defined in the electrode structure under the plurality of opening holes, and exposing pad areas of the electrode layers, respectively. The plurality of opening holes are disposed by being distributed in a plurality of rows arranged in a second direction intersecting with the first direction.

Abstract: A leadframe includes a first die attach pad (“DAP”) having a first longitudinally extending edge surface and a second DAP having a first longitudinally extending edge surface. The second DAP is positioned with the first longitudinally extending edge surface thereof in adjacent, laterally and vertically spaced relationship with the first longitudinally extending edge surface of the first DAP.

Abstract: The present disclosure concerns an integrated circuit comprising a substrate, the substrate comprising a first region having a first thickness and a second region having a second thickness smaller than the first thickness, the circuit comprising a three-dimensional capacitor formed inside and on top of the first region, and at least first and second connection terminals formed on the second region, the first and second connection terminals being respectively connected to first and second electrodes of the three-dimensional capacitor.

Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, first and second insulating members, and a first member. The third electrode includes a first electrode portion. The first electrode portion is between the first and second electrodes. The first semiconductor layer includes first, second, third, fourth, and fifth partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The first insulating member includes first and second insulating regions. The second insulating member includes first and second insulating portions. The first insulating portion is between the fourth partial region and the first insulating region. The second insulating portion is between the fifth partial region and the second insulating region. The second semiconductor layer includes first, second, and third semiconductor portions.

Abstract: Methods of doping a semiconductor material are disclosed. Some embodiments provide for conformal doping of three dimensional structures. Some embodiments provide for doping with high concentrations of boron for p-type doping.

Abstract: A method of making a secure integrated-circuit system comprises providing a first integrated circuit in a first die having a first die size and providing a second integrated circuit in a second die. The second die size is smaller than the first die size. The second die is transfer printed onto the first die and connected to the first integrated circuit, forming a compound die. The compound die is packaged. The second integrated circuit is operable to monitor the operation of the first integrated circuit and provides a monitor signal responsive to the operation of the first integrated circuit. The first integrated circuit can be constructed in an insecure facility and the second integrated circuit can be constructed in a secure facility.

Abstract: Apparatus and other embodiments associated with high speed and high breakdown voltage MOS rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, an enclosed deep trench in ring shape surrounds a vertical MOS structure plus a shallow trench gate in the center to create a device with very high breakdown voltage and very low leakage current. This structure is extended to multiple deep trenches and shallow trenches alternating each other.

Abstract: A semiconductor light emitting element includes: an n-type clad layer of an n-type aluminum gallium nitride (AlGaN)-based semiconductor material; an active layer of an AlGaN-based semiconductor material provided on a first top surface of the n-type clad layer; and an n-side electrode provided on a second top surface of the n-type clad layer adjacent to the first top surface. The n-side electrode includes a first metal layer on the second top surface containing titanium (Ti) and a second metal layer on the first metal layer containing aluminum (Al). A root-mean-square roughness (Rq) of a top surface of the second metal layer is 5 nm or less.

Abstract: A semiconductor device includes a base structure including a lower level via and a lower level dielectric layer, a conductive pillar including an upper level line and an upper level via disposed on the lower level via, and a protective structure disposed between the lower level via and the upper level line. The protective structure includes a material having an etch rate less than or equal to that of the lower level via.

Abstract: Provided are a tin oxide layer, a thin film transistor (TFT) having the same as a channel layer, and a method for manufacturing the TFT. The TFT comprises a gate electrode, a tin oxide channel layer disposed on the gate electrode and being a polycrystalline thin film with preferred orientation in a [001] direction, a gate insulating film disposed between the gate electrode and the channel layer, and source and drain electrodes electrically connected to both ends of the channel layer, respectively.

Abstract: A semiconductor device according to an embodiment is attached to a radiator and includes a heat-generating electronic component, a sealing part sealing the electronic component, a lead member that includes an inner lead part sealed with the sealing part and an outer lead part exposed from the sealing part, and a lead member that includes an inner lead part sealed with the sealing part and an outer lead part exposed from the sealing part. The inner lead part has a heat-dissipating end part that releases heat propagating from the outer lead part to the radiator and an electrical connecting part that is positioned between the heat-dissipating end part and the outer lead part and is electrically connected to the main electrode of the electronic component.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first insulating layer positioned above the substrate, a second insulating layer positioned above the first insulating layer, a plurality of first conductive features positioned in the first insulating layer and the second insulating layer, and an alleviation structure positioned between the first insulating layer and the second insulating layer.

Abstract: An integrated circuit includes an active zone having a center portion adjoining a first side portion and a second side portion. A first transistor having a gate formed over one of the first channel regions in the center portion has a first threshold-voltage. A second transistor having a gate formed over one of the second channel regions in the center portion has a second threshold-voltage. A third transistor having a gate formed over one of the third channel regions in the first side portion has a third threshold-voltage. A fourth transistor having a gate formed over one of the fourth channel regions in the second side portion has a fourth threshold-voltage. A first average of the first threshold-voltage and the second threshold-voltage is larger than a second average of the third threshold-voltage and the fourth threshold-voltage by a predetermined threshold-voltage offset.

Abstract: A method of forming the fin structure that includes forming a replacement gate structure on a channel region of the at least one replacement fin structure; and forming an encapsulating dielectric encapsulating the replacement fin structure leaving a portion of the replacement gate structure exposed. The exposed portion of the replacement gate structure is etched to provide an opening through the encapsulating dielectric to the replacement fin structure. The replacement fin structure is etched selectively to the dielectric to provide a fin opening having a geometry dictated by the encapsulating dielectric. Functional fin structures of a second semiconductor material is epitaxially grown on the growth surface of the substrate substantially filling the fin opening.

Abstract: A package substrate including a first redistribution structure, a first bonding layer, a core, a second bonding layer and a second redistribution structure in a sequential order is provided. The first redistribution structure has a first redistribution surface and a first bonding pad disposed on the first redistribution surface. The second redistribution structure has a second redistribution surface and a second bonding pad disposed on the second redistribution surface. The core has a first core pad disposed on a first core surface, and a second core pad disposed on a second core surface opposite to the first core surface. The first core pad and the second core pad are directly bonded to first bonding pad and the second bonding pad, respectively. The first core pad and the second core pad are offset from first bonding pad and the second bonding pad, respectively. The first bonding pad and the first core pad are embedded in the first bonding layer.

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

Abstract: The present invention relates to organic electroluminescent devices comprising a light-emitting layer B comprising a host material, a phosphorescence material and a emitter material, which exhibits a narrow—expressed by a small full width at half maximum (FWHM)—green emission at an emission maximum of 500 to 560 nm. Further, the present invention relates to a method for generating green light by means of an organic electroluminescent device according to the present invention.

Abstract: A semiconductor package includes a frame having a through-opening, a first semiconductor chip disposed in the through-opening and having a first active surface on which a first connection pad is disposed and a first inactive surface opposing the first active surface, a second semiconductor chip disposed on the first semiconductor chip and having a second active surface on which a second connection pad is disposed and a second inactive surface opposing the second active surface, first and second bumps electrically connected to the first and second connection pads, respectively, first and second dummy bumps disposed on a same level as levels of the first and second bumps, respectively, first and second posts electrically connected to the first and second bumps, respectively, a connection member including a redistribution layer electrically connected to each of the first and second posts, and a dummy post disposed between the frame and the connection member.

Abstract: A parallel redundant system comprises a substrate, a first circuit disposed over the substrate, a first conductor disposed at least partially in a first layer over the substrate and wire routed to the first circuit, a second circuit disposed over the substrate, the second circuit redundant to the first circuit, a second conductor disposed in a second layer over the substrate and electrically connected to the second circuit, the second conductor disposed at least partially over the first conductor, a dielectric layer disposed at least partially between the first layer and the second layer, and a laser weld electrically connecting the first conductor to the second conductor.

Abstract: A display device includes: a circuit element layer comprising a transistor; a display element layer comprising a first electrode connected to the transistor, a second electrode facing the first electrode, an organic pattern between the first electrode and the second electrode, a pixel defining layer having an opening exposing the first electrode, an auxiliary electrode spaced apart from the opening to cover a portion of the pixel defining layer and connected to the second electrode, a first protection pattern covering the second electrode, and a second protection pattern covering the first protection pattern; and an encapsulation layer covering the display element layer, wherein the first protection pattern and the second protection pattern have stress in directions different from each other.