Abstract: Methods and structures for forming vias are provided. The method includes forming a structure that includes an odd line hardmask and an even line hardmask. The odd line hardmask and the even line hardmask include different hardmask materials that have different etch selectivity with respect to each other. The method includes patterning vias separately into the odd line hardmask and the even line hardmask based on the different etch selectivity of the different hardmask materials. The method also includes forming via plugs at the vias. The method includes cutting even line cuts and odd line cuts into the structure. The even line cuts and the odd line cuts are self-aligned with the vias. The vias are formed at line ends of the structure.

Abstract: A chip part includes a chip main body which has a first main surface at one side, a second main surface at the other side and side surfaces that connect the first main surface and the second main surface and which includes a terminal electrode exposed from the first main surface, and an outer surface resin which exposes the first main surface of the chip main body and covers an outer surface of the chip main body.

Abstract: A substrate with an electronic component embedded therein includes a core substrate including an insulating body having a first surface and a second surface, opposite to the first surface, a first wiring layer embedded in the insulating body such that one surface thereof is exposed from the first surface, and a second wiring layer disposed on the insulating body to protrude on the second surface, the core substrate having a cavity penetrating a portion of the insulating body from the first surface toward the second surface and having a stopper layer as a bottom surface thereof; an electronic component disposed on the stopper layer in the cavity; a first insulating material covering at least a portion of each of the core substrate and the electronic component; and a third wiring layer disposed on the first insulating material.

Abstract: A light emitting device having first, second and third dimensions that are orthogonal may include a light emitting semiconductor device configured to emit light via a first surface in a plane formed by the first and second dimensions. The light emitting device may further include a wavelength converting structure disposed on the first surface of the light emitting semiconductor device, the wavelength converting structure extending beyond the light emitting semiconductor device in the first dimension and the light emitting semiconductor device extending beyond the wavelength converting structure in the second dimension. The light emitting device may further include one or more optical extraction features in at least one gap formed by the wavelength converting structure extending beyond the light emitting semiconductor structure in the first dimension and/or formed by the light emitting semiconductor structure extending beyond the wavelength converting structure in the second dimension.

Abstract: A cascode transistor device includes a semiconductor substrate, and a first and a second compound semiconductor transistors. The first compound semiconductor transistor includes a first n-type doping layer, a first p-type doping layer and a second n-type doping layer sequentially disposed on the semiconductor substrate. The second compound semiconductor transistor includes a third n-type doping layer, a second p-type doping layer and a fourth n-type doping layer sequentially disposed on the second n-type doping layer. Each of these doping layers is formed with an exposed metal contact. The exposed metal contact on the second n-type doping layer is electrically connected to the exposed metal contact on the third n-type doping layer.

Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.

Abstract: A light-emitting device is provided, which includes a first semiconductor structure, an active structure, a second semiconductor structure, and a first blocking layer. The first semiconductor structure has a first conductivity type. The active structure is on the first semiconductor structure and has a first dopant. The second semiconductor structure is on the active structure and has a second conductivity type different from the first conductivity type. The first blocking layer is between the second semiconductor structure and the active structure. The first blocking layer has the first dopant with a first doping concentration decreasing along a depth direction from the second semiconductor structure to the first semiconductor structure.

Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.

Abstract: A light-emitting device and an electrode thereof are provided. The electrode includes a first electrode and an auxiliary electrode. The auxiliary electrode is disposed on the first electrode and covers a portion of the first electrode. A material of the first electrode is a metal oxide or alkali metal salt doped with a metal. A material of the auxiliary electrode includes a metal or an alloy thereof.

Abstract: A laser bonding method includes forming a bonding part including an adhesive layer and a conductive particle disposed within the adhesive layer on a substrate; aligning a bonding target by disposing the bonding target on a surface of the bonding part opposite the substrate; disposing a pressing part on a surface of the bonding target that is opposite to the bonding part and pressing the bonding target onto the bonding part through the pressing part; heating the bonding target by irradiating at least the pressing part with a laser and conducting heat from the pressing part to the bonding target and from the bonding target to the bonding part; and bonding together the bonding part and the bonding target by the heat conducted from the bonding target to the bonding part so that the conductive particle electrically connects the substrate and the bonding target. The pressing part may be removed.

Abstract: Integrated chips and methods of forming the same include forming lines of alternating first and second sacrificial fills in a film. A dielectric cut is formed in at least one of the first sacrificial fills. A dielectric cut is formed in at least one of the second sacrificial fills. Remaining first and second sacrificial fill material is replaced with a conductive material. The film is replaced with a final dielectric material.

Abstract: A semiconductor device, includes a channel region, and a source/drain region adjacent to the channel region. The source/drain region includes a first epitaxial layer, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer, and the first epitaxial layer is made of SiAs.

Abstract: A semiconductor device and its manufacturing method are presented, relating to semiconductor technology. The manufacturing method comprises: providing a substrate structure comprising a substrate, a source region on the substrate, and a gate structure on the source region; forming cavities on two opposing sides of the gate structure; epitaxially growing electrodes in the cavities, with each electrode comprising an electrode body and an amorphous layer on the electrode body; forming an dielectric layer on the substrate structure covering the electrodes and the gate structure; etching the dielectric layer to form a contact hole exposing the amorphous layer; forming a conductive adhesive layer on the bottom and on the side of the contact hole; and forming a contact component on the conductive adhesive layer filling the contact hole. In this semiconductor device, the adhesive layer may be directly formed on the amorphous layer, resulting in improved performance of the device.

Abstract: An integrated circuit (IC) die is provided, which includes a die body; electrostatic discharge (ESD) circuitry formed in the die body; contact pads exposed on an active side of the die body; a first conductive tower formed in the die body and electrically coupling a first contact pad to the ESD circuitry. The first conductive tower comprises first, second, third, and fourth segments formed from metal layers of the die body; a first via electrically coupling the first segment to the second segment; a second via electrically coupling the first segment to the third segment; a third via electrically coupling the second segment to the fourth segment; and a fourth via electrically coupling the third segment to the fourth segment, the second segment electrically parallel with the third segment. The IC die further comprises at least a first data line disposed between the first, second, third, and fourth segments.

Abstract: A display device includes a substrate, a plurality of active pixels, and a plurality of passive pixels. The substrate has a first display region and a second display region connected to the first display region. The plurality of passive pixels are disposed on the first display region. The plurality of active pixels are disposed on the second display region.

Abstract: A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element.

Abstract: Techniques for forming quantum circuits, including connections between components of quantum circuits, are presented. A trench can be formed in a dielectric material, by removing a portion of the dielectric material and a portion of conductive material layered on top of the dielectric material, to enable creation of circuit components of a circuit. The trench can define a regular nub or compensated nub to facilitate creating electrical leads connected to the circuit components on a nub. The compensated nub can comprise recessed regions to facilitate depositing material during evaporation to form the leads. For compensated nub implementation, material can be evaporated in two directions, with oxidation performed in between such evaporations, to contact leads and form a Josephson junction. For regular nub implementation, material can be evaporated in four directions, with oxidation performed in between the third and fourth evaporations, to contact leads and form a Josephson junction.

Abstract: A deposition system that mitigates feathering in a directly deposited pattern of organic material is disclosed. Deposition systems in accordance with the present disclosure include an evaporation source, an electrically conductive shadow mask, and an electrically conductive field plate. The source imparts a negative charge on vaporized organic molecules as they are emitted toward a target substrate. The source and substrate are biased to produce an electric field having field lines that extend normally between them. The shadow mask and field plate are located between the source and substrate and each functions as an electrostatic lens that directs the charged vapor molecules toward propagation directions aligned with the field lines as the charged vapor molecules approach and pass through them.

Abstract: A display device includes a substrate having a display area, a peripheral area at least partially surrounding the display area, and a pad area within the peripheral area. A plurality of data lines is disposed within the display area. A plurality of connection wirings is disposed within the display area, connected to the plurality of data lines, and configured to transmit a data signal from the pad area to the plurality of data lines. Each of the plurality of connection wirings includes a plurality of branches that protrude from the connection wirings in a direction perpendicular to a direction in which the connection wirings are primarily extended.

Abstract: Disclosed herein is a semiconductor device package including: a body including a cavity; a semiconductor device disposed in the cavity; a light transmitting member disposed on the cavity; and an adhesive layer which fixes the light transmitting member to the body, wherein the cavity includes a stepped portion on which the light transmitting member is disposed, the stepped portion includes a first bottom surface and a third bottom surface spaced apart from each other in a first direction, a second bottom surface and a fourth bottom surface spaced apart from each other in a second direction perpendicular to the first direction, a first connecting portion in which the first bottom surface and the second bottom surface are connected to each other, a second connecting portion in which the second bottom surface and the third bottom surface are connected to each other, a third connecting portion in which the third bottom surface and the fourth bottom surface are connected to each other, and a fourth connecting porti