Patents Examined by Justin R Knapp
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Patent number: 11726867Abstract: A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.Type: GrantFiled: May 11, 2022Date of Patent: August 15, 2023Assignee: Micron Technology, Inc.Inventors: Harish Reddy Singidi, Kishore Kumar Muchherla, Xiangang Luo, Vamsi Pavan Rayaprolu, Ashutosh Malshe
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Patent number: 11726874Abstract: A request to retrieve user data stored at a memory device is received and a first error control operation associated with the user data is performed. An indication of a failure of the first error control operation is received, and in response, a subset of system data stored at the memory device is identified. A second error control operation is performed on the subset of the system data to retrieve the subset of the system data stored at the memory device, and the user data is read by using the subset of the system data retrieved based on the performing of the second error control operation.Type: GrantFiled: March 1, 2021Date of Patent: August 15, 2023Assignee: Micron Technology, Inc.Inventors: Vamsi Rayaprolu, Sivagnanam Parthasarathy, Sampath K. Ratnam, Peter Feeley, Kishore Kumar Muchherla
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Patent number: 11728829Abstract: A method of decoding a polar coded signal includes determining channel reliabilities for a plurality of polar coded bit channels in a data communication system including a plurality of frozen bit channels and non-frozen bit channels, selecting a frozen bit channel, calculating a likelihood value for a bit estimate associated with the frozen bit channel, generating a hard decision value for the bit estimate in response to the likelihood value, comparing the hard decision value for the bit estimate to a known value of a frozen bit transmitted on the frozen bit channel, in response to determining that the hard decision value for the bit estimate differs from the known value of the frozen bit transmitted on the frozen bit channel, updating an accumulated uncertainty, comparing the accumulated uncertainty to a threshold, and determining that a decoding error has occurred in response to the comparison.Type: GrantFiled: April 11, 2022Date of Patent: August 15, 2023Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Dennis Hui, Yufei Blankenship
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Patent number: 11722151Abstract: Methods, systems, and apparatuses include receiving a codeword stored in a memory device. Energy function values are determined for bits of the codeword based on soft information for the bits of the codeword. A bit of the codeword is flipped when the energy function values for a bit of the codeword satisfies a bit flipping criterion. A corrected codeword that results from the flipping of the bits is returned.Type: GrantFiled: August 9, 2021Date of Patent: August 8, 2023Assignee: MICRON TECHNOLOGY, INC.Inventors: Mustafa N. Kaynak, Sivagnanam Parthasarathy
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Patent number: 11714705Abstract: A memory circuit includes: a memory configured to store a data unit and parity bits, the parity bits including data parity bits based on the data unit and write address parity bits based on a write address associated with the stored data unit; a write address port configured to receive the write address for the stored data unit; a first decoding circuit configured to determine when a data error exists based on the stored data unit and the data parity bits; a second decoding circuit configured to generate a decoded write address from a read address and the write address parity bits; and an error detecting circuit configured to determine when an address error exists based on a comparison of the decoded write address to the read address.Type: GrantFiled: June 30, 2022Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Saman M. I. Adham, Ramin Shariat-Yazdi, Shih-Lien Linus Lu
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Patent number: 11714719Abstract: Apparatus for tiered storage of data in a storage network. In an example of operation, a computing device receives a data object for storage and forwards the data object for storage in a first plurality of memory devices of a first memory type. The computing device determines a system level storage efficiency for the data object based, at least in part, on a data attribute associated with the data object. The computing device further selects, based at least in part on the system level storage efficiency preference, a second plurality of memory devices comprised of a second memory type. The computing device determines error encoding parameters based on the second plurality of memory devices, retrieves the data object from the first plurality of memory devices, and encodes the data object with the error encoding parameters to generate a plurality of encoded data slices for storage in the second plurality of memory devices.Type: GrantFiled: September 30, 2022Date of Patent: August 1, 2023Assignee: Pure Storage, Inc.Inventors: S. Christopher Gladwin, Timothy W. Markison, Greg R. Dhuse, Thomas F. Shirley, Jr., Wesley B. Leggette, Jason K. Resch, Gary W. Grube
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Patent number: 11709733Abstract: Data to be stored at a memory sub-system can be received from a host system. A portion of the host data that includes user data and another portion of the host data that includes system metadata can be determined. A mapping for a data structure can be received that identifies locations of the data structure that are fixed with respect to an encoding operation and locations of the data structure that are not fixed with respect to the encoding operation. The data structure can be generated for the user data and system metadata based on the mapping, and an encoding operation can be performed on the data structure to generate a codeword.Type: GrantFiled: March 29, 2021Date of Patent: July 25, 2023Assignee: Micron Technology, Inc.Inventors: Tingjun Xie, Ying Yu Tai, Jiangli Zhu
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Patent number: 11709734Abstract: Methods, systems, and apparatus for error correction with syndrome computation in a memory device are described. A first syndrome for first encoded data is generated in a memory device. The first syndrome and the first encoded data are transmitted to a controller that is coupled with the memory device. A second syndrome for first and second encoded data is generated. The first encoded data and the second encoded data are interrelated according to an error correction code. The second syndrome is transmitted to the controller without the second encoded data and the controller is to decode the first encoded data based on at least one of the first syndrome, the second syndrome, or a combination thereof.Type: GrantFiled: April 30, 2021Date of Patent: July 25, 2023Assignee: MICRON TECHNOLOGY, INC.Inventors: Mustafa N. Kaynak, Patrick R. Khayat, Sivagnanam Parthasarathy
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Patent number: 11705992Abstract: An infrastructure equipment that transmits signals representing data via a wireless access interface to a communications device and receives signals representing data via the wireless access interface from the communications device in accordance with a time divided structure in which the wireless access interface is divided into a plurality of repeating time units. The infrastructure equipment provides, in each of a first plurality of the time units, one of a plurality of control channels each configured to schedule one of a plurality of data channels, and provides, in each of a second plurality of time units of the signal transmitted to the communications device, one of the plurality of data channels, the plurality of data channels being formed of one or more bundles of data channels, wherein the infrastructure equipment transmits a bundle status indicator in one or more of the plurality of control channels.Type: GrantFiled: May 23, 2022Date of Patent: July 18, 2023Assignee: SONY GROUP CORPORATIONInventors: Shin Horng Wong, Martin Warwick Beale
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Patent number: 11695429Abstract: A method for encoding may include receiving, at an encoder, a series of data bits, performing, at the encoder, first transition encoding on the data bits to generate an encoded series of data bits based on a key, performing, at the encoder, protection encoding on the key to generate key protection data, performing, at the encoder, second transition encoding on the key protection data to generate encoded key protection data, and transmitting an encoded series of transmission bits to a receiver, the encoded series of transmission bits including the encoded series of data bits and the encoded key protection data.Type: GrantFiled: November 1, 2021Date of Patent: July 4, 2023Assignee: Samsung Display Co., Ltd.Inventors: Aliazam Abbasfar, Amir Amirkhany
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Patent number: 11663076Abstract: A method for memory protection includes receiving a burst-write instruction that includes data and a burst-write address. The data are segmented into a plurality of data blocks. One or more bits of the burst-write address, or a hash of the burst-write address are concatenated to respective data blocks to obtain data-and-write-address-bit (DWAB) segments. A SECDED ECC is executed on respective DWAB segments to generate a corresponding plurality of sets of parity bits (DWAB-PB). Respective DWAB-PB are concatenated to the corresponding data block to generate corresponding forward-error-correction (FEC) blocks, none of the FEC blocks including the burst-write address or the hash of the burst-write address. A burst-write command and a respective portion of a respective FEC block is sent to respective memory devices during a plurality of beats until all of the beats of the burst-write have been sent.Type: GrantFiled: May 26, 2022Date of Patent: May 30, 2023Assignee: Microchip Technology Inc.Inventor: Peter John Waldemar Graumann
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Patent number: 11650883Abstract: A method includes, determining, for a batch rebuild process regarding a first batch threshold number of encoded data slices of a set of encoded data slices that need rebuilding, a target storage unit of target storage units of a set of storage units of the storage network is unavailable, where a data segment of data is dispersed storage error encoded into the set of encoded data slices, the set of encoded data slices is stored in the set of storage units, and the first batch threshold number of encoded data slices is to be stored in the target storage units. When the target storage unit becomes available before a second batch rebuild threshold number of encoded data slices of the set of encoded data slices is met, the method includes executing the batch rebuild process for the first batch threshold number of encoded data slices.Type: GrantFiled: April 27, 2022Date of Patent: May 16, 2023Assignee: Pure Storage, Inc.Inventors: Niall J. McShane, Andrew D. Baptist, Ravi V. Khadiwala
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Patent number: 11646823Abstract: A method, apparatus, and computer-readable medium for transmitting coded messages to a receiving device including constructing a data vector including a plurality of data bits, transforming the data vector into a u-domain vector, applying a mask to the u-domain vector, encoding the masked u-domain vector with polar encoding to generate a transmission vector, and transmitting, to the receiving device, the transmission vector.Type: GrantFiled: February 6, 2019Date of Patent: May 9, 2023Assignee: QUALCOMM IncorporatedInventors: Kai Chen, Liangming Wu, Changlong Xu, Jian Li, Hao Xu
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Patent number: 11640337Abstract: User data and redundant codes are stored in a distributed manner, and data is read while suppressing performance degradation due to the occurrence of a failure. If a first node in a distributed storage system receives a read request from a host to read the user data when a storage device of its own node is blocked, the first node executes a first collection read request which requests recovery of data from the secondary redundant code corresponding to target data of the read request; and if at least part of the target data has failed to be recovered according to the first collection read request, regarding insufficient data among a plurality of pieces of data which are necessary to recover the target data by using the primary redundant code, the first node executes a second collection read request which requests recovery of the insufficient data from the secondary redundant code.Type: GrantFiled: September 10, 2021Date of Patent: May 2, 2023Assignee: HITACHI, LTD.Inventors: Kazuki Mizukami, Hiroaki Miyata
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Patent number: 11640357Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to facilitate read-modify-write support in a victim cache. An example apparatus includes a first storage coupled to a controller, a second storage coupled to the controller and parallel coupled to the first storage, and a storage queue coupled to the first storage, the second storage, and to the controller, the storage queue to obtain a memory operation from the controller indicating an address and a first set of data, obtain a second set of data associated with the address from at least one of the first storage and the second storage, merge the first set of data and the second set of data to produce a third set of data, and provide the third set of data for writing to at least one of the first storage and the second storage.Type: GrantFiled: May 22, 2020Date of Patent: May 2, 2023Assignee: Texas Instruments IncorporatedInventors: Naveen Bhoria, Timothy David Anderson, Pete Michael Hippleheuser
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Patent number: 11640333Abstract: Systems and methods for increasing the endurance of a solid state drive are disclosed. The disclosed systems and methods can assign different levels of error protection to a plurality of blocks of the solid state drive. The disclosed methods can provide a plurality of error correction mechanisms, each having a plurality of corresponding error correction levels and associate a first plurality of blocks of the solid state drive with a first zone and a second plurality of blocks of the solid state drive with a second zone. The disclosed methods can assign a first error correction mechanism and a first corresponding error correction level to the first zone and can assign a second error correction mechanism and a second corresponding error correction level to the second zone.Type: GrantFiled: October 14, 2021Date of Patent: May 2, 2023Assignee: Western Digital Technologies, Inc.Inventors: Ashish Singhai, Vijay Karamcheti, Ashwin Narasimha
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Patent number: 11641254Abstract: An electronic device (such as an access point) is described. This electronic device transmits an orthogonal frequency division multiple access (OFDMA) frame to a recipient electronic device (such as a client or a station). The OFDMA frame includes multiple predefined resource units (RUs) allocated to the recipient electronic device in a set of predefined RUs having associated frequency bandwidths. Moreover, the multiple predefined RUs include two or more first predefined RUs having a first number of tones less than a predefined amount, or two or more second predefined RUs having a second number of tones greater than or equal to the predefined amount. For example, the predefined amount may include 242 tones. Note that the multiple predefined RUs may have the same or different numbers of tones. Moreover, the electronic may receive an acknowledgment or a block acknowledgment from the recipient electronic device.Type: GrantFiled: March 8, 2021Date of Patent: May 2, 2023Assignee: Apple Inc.Inventors: Tianyu Wu, Yong Liu, Jinjing Jiang, Jarkko L. Kneckt, Lochan Verma, Qi Wang, Su Khiong Yong, Anuj Batra
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Patent number: 11636007Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. A memory system may include a memory device and a memory controller configured to, when receiving from the host a flush command instructing to flush data cached in a data cache to the memory device, flush first data cached in the data cache, the first data having a size smaller than a size of the reference write unit, to the memory device, write a first parity associated with the first data to a parity memory block, update a value of a parity location pointer indicating a location where the first parity is written, and set a parity write flag indicating whether the parity at the location pointed by the parity location pointer is valid.Type: GrantFiled: April 2, 2021Date of Patent: April 25, 2023Assignee: SK hynix Inc.Inventor: Min Kyung Choi
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Patent number: 11637569Abstract: This application provides a polar coding method, a polar decoding method, and an apparatus. A transmit end obtains K to-be-coded bits and an index set including K polar channels, where a value set of K1 indexes in the set of the K indexes or a value set of K2 indexes in the set of the K indexes is determined based on a value set of K2 of the K to-be-coded bits, and the value set of the K1 indexes and the value set of the K2 indexes are complementary sets of each other; and performs polar coding on K1 to-be-coded bits. In comparison with a conventional polar coding method and a conventional polar decoding method, the polar coding method and the polar decoding method provided in this application can achieve an effect of reducing a bit rate. A simulation result indicates that the method has better performance.Type: GrantFiled: July 16, 2021Date of Patent: April 25, 2023Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Tianhang Yu, Gongzheng Zhang, Rong Li, Zhaoyang Zhang
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Patent number: 11632137Abstract: A method includes receiving a request for host data, receiving a codeword that is associated with the host data, performing a decoding operation for a first portion of the codeword to generate a segment of decoded data, determining whether the segment of the decoded data satisfies the request for the host data, and in response to determining that the segment of the decoded data satisfies the request for the host data, terminating the decoding operation for remaining portions of the codeword.Type: GrantFiled: April 26, 2021Date of Patent: April 18, 2023Assignee: Micron Technology, Inc.Inventors: Tingjun Xie, Ying Yu Tai, Jiangli Zhu