Abstract: A device is described for electronically executing a mathematical operation, being Z=KA+(1-K)B. It is also described how this device or how several of such devices can be used for the design of a number of realizations, such as a recursive filter, a digital mixer etc. The basic idea is the electronic implementation of a mathematical function for binary variables.

Abstract: A decoder circuit is provided which employs digital sampling and correlation apparatus to detect the presence of a received tone signal exhibiting a predetermined frequency. Samples of received tone signals are taken and, in effect, multiplied by a substantially rectangular observation window which includes a bite interval of selected duration and location therein. A correlator correlates the windowed samples to detect samples corresponding to the predetermined frequency (main lobe frequency). A significant decrease in undesired side lobe response is thus achieved.

Abstract: A microprocessor-based motor control system operates the rapid advance motor on a slide transfer machine to carry out rapid traverse motions in minimal time. A velocity profile is stored during the acceleration portion of the move and this data is employed to determine when deceleration should begin and to control velocity during the deceleration portion of the move. A position feedback circuit having programmable resolution is employed to develop the velocity profile.

Abstract: A procedure for use with a data acquisition system and an array processor for real time processing of the acquired data. Rather than utilize the array processor in its normal mode to process one array before moving on to the next, processing of subportions of a given array is interleaved with inputting of acquired data sets for the next array. The size of the subgroup, the number of data sets in the array, the number of channels to be processed, the nature of the process to be performed and the speed at which it can be performed are balanced in such a way that (a) processing of a subgroup is completed at about the time the next set is ready for input, and (b) at the completion of processing of the last subgroup within a given array, the last set of the next array is ready for input, so that processing of the next array commences immediately.

Abstract: A method and apparatus are described for controlling access of a user of a postal value computing system to the computation of special fees. A directory memory stores a special fee control byte which is combined with a rate fee screen byte that is generated by the system to represent the special fee computations requested in response to actuation of the keyboard. The combining of the bytes employs a bit for bit AND operation with the result stored as a modified rate screen byte for use in the subsequent special fee computations. Access may then be granted or denied, depending upon the special fee control byte.

Abstract: High speed serial data bits of a data stream are received, stored, shifted and compared in parallel to bit contents of a known correlation word. For each bit match a known signal change is provided on a common terminal. High speed current or voltage changes on the common terminal are proportional to the number of matching bits and are monitored to detect presence of the correlation word in the received data stream. The circuit has minimum number of components and built-in temperature compensation.

Abstract: The invention disclosed, a microprocessor based exposure computer, automates the time consuming and tedious calibrations and calculations which were necessary to reproduce high quality copy in the field of graphic arts. The automated nature of the invention includes the ability of the device disclosed to perform a self calibrating function which greatly reduces the set-up time of the instrument which in the past has required trial and error calibrations involving the repeated manipulation of a gray scale of varying density or other variable light attenuator.

Abstract: A system for gathering topographic data for use in computer generation of topographic maps of various forms. This system includes equipment mounted in an aircraft which can be flown over a terrain area which is to be surveyed. The equipment comprises a low frequency radar which is capable of penetrating foliage in the survey area for generating a signal representative of the distance from the aircraft to the terrain surface, a precision altimeter that produces a signal representative of the altitude of the aircraft with respect to a reference plane such as sea level, temperature and humidity sensors for producing signals representative of those quantities, a clock for producing a signal representative of a standard time, and a digital recorder for recording the previously named signals which are produced during over flight of a survey area.

Abstract: A retail terminal to register merchandise data such as a price of merchandise, amount of merchandise, a merchandise code and a merchandise name in a department store or a retail store is disclosed. The retail terminal includes a data buffer for temporarily storing the merchandise data of a plurality of items of merchandise item by item, the merchandise data stored item by item are summed upon the depression of a total key when the account for a customer has been completed and the sum is stored in a memory. Upon the depression of a correction key, the data temporarily stored in the data buffer are sequentially and retrogressively cleared item by item. In this manner, the correction for the plurality of items of merchandise is simplified.

Abstract: An acceleration schedule, from which data is derived for use in calculating fuel flow during acceleration of a gas turbine engine, is modified each time the engine surges so as to avoid future surges.

Abstract: A monolithic convolver circuit making extensive use of "pipelined" architecture to ensure high speed by concurrency of processing, and having a repetitive stage to facilitate chip layout and manufacture. The circuit includes a multiplier and an adder in each stage. The adders produce a sequence of summation terms concurrently and include shift registers to move and accumulate the results of convolution. The adders produce only partial sums at each stage, to increase processing speed. Full computation of carries is deferred until the very end, and performed in a separate conditional sum adder.

Abstract: In an airborne target acquisition and tracking system having a stabilization axis and an optical axis in which a slight mechanical misalignment is present, an apparatus and method for electronically compensating for such misalignment. A roll rate sensing circuit in the system produces a signal when the aircraft rolls. A yaw scaling factor circuit and a pitch scaling factor circuit operate on the roll rate signal and apply scaled versions thereof to the yaw rate servo subsystem and the pitch rate servo subsystem respectively to cancel a yaw rate error signal and a pitch rate error signal produced by the mechanical misalignment. The required scale factors are automatically adjusted by use of a calibrate mode by microprocessors that calculate the ratio of yaw and pitch error signals, generated by artifically rolling the system, to the roll rate signal also generated. The measured ratios are stored in non-volatile memories functioning when the system is in the operate mode.

Abstract: A plurality of electrical load switches of the type operable to at least two operating conditions by the actuation of an operating member are connected in respective motor vehicle load circuits and are mounted in a switching unit having an actuating mechanism for actuating the switch operating members that is selectively locatable in each of a plurality of switch operating positions in each of which it is in register with an operating member. The switching unit is controlled by a microprocessor that effects the locating of the actuating mechanism in the switch operating position in which it may actuate the operating member of a load switch selected to be operated and the operating of the actuating mechanism when so located in response to function select electrical signals that indicate the load switches selected for operation.

Abstract: A new and improved straight line coordinates generator to determine and generate the coordinates of a group of lattice points [P.sub.k (k=1, 2, . . . , n-1)] to simulate an actual line defined by connecting the two lattice points P.sub.O (X.sub.o, Y.sub.o) and P.sub.n (X.sub.n, Y.sub.n), on a secondary coordinates face comprises registers, adders, comparators, a clock generator gate circuit, X-coordinate counter for determining X-coordinate values, Y-coordinate counter for determining Y-coordinate values, an initializing device for setting the registers with initial normalizing values and a generator for sequentially generating each X and Y coordinate of the lattice points to simulate the line. The circuit arrangement of the straight line coordinates generator is simplified by eliminating the need for decimal points in determining the coordinates of the lattice points to be lightened or highlighted to form the simulated line.

Abstract: A method is disclosed for editing seismic traces gathered by large multichannel collection systems using a pattern analysis of the noise spectrum of each trace. Analysis is limited to only a small time window, say the last second of the trace. In that way a minimum number of quantitative variables and mathematical manipulations are required to carry out the invention. On-site as well as off-site, processing of the traces in accordance with the method of the present invention, is contemplated.

Abstract: There is shown and described a floating point processor having improved architecture and configuration. The floating point processor (FPP) performs addition, subtraction, multiplication, division and square root operations. Usually, the square root operation is not built into the FPP hardware because of the increased complexity of the design, and, therefore, cost of the goods. Rather, the square root operation is usually implemented by firmware or software. The device of this invention performs the floating point square root operation in hardware rather than in software or firmware while adding very little additional hardware to existing circuitry which is required for the basic addition, subtraction, multiplication and division operations. In addition, the operations are performed as rapidly as, or more rapidly than, prior art devices.

Abstract: The ability of a gas turbine engine to recover from surge is enhanced by implementing a closed loop control mode wherein fuel flow is varied as a function of the ratio of the rate of change of engine gas generator speed to compressor discharge pressure.

Abstract: A method and apparatus for the arithmetic division operation is disclosed in which a set of multiples of the divisor are stored in an associative memory in addresses which match the respective multiples. The most significant byte of the numerator is then compared to the contents of each associative entry. A flag is generated signifying that the corresponding entry is less than or equal to the most significant byte of the numerator. After the flags have been generated, the address of the last flag which is on, is selected. This provides a trial "digit out", which is used to address the true table of multiples and select a value which is subtracted from the left-digit-shifted numerator (or intermediate result). If no underflow condition results, the trial "digit out" is valid and should be stored and the next iteration started. For an underflow condition, the "digit out" is decremented and stored, the X1 multiple is added to the numerator and the next iteration is carried out.

Abstract: A surge control system is disclosed for centrifugal compressors which utilizes an algorithm to calculate a desired orifice differential pressure and compare the calculated result with an actual differential pressure. A controller is provided for operating a blow-off valve to bring the actual differential pressure to the calculated differential pressure.

Abstract: A function generator responsive to clock pulses for developing an analog signal in the form of a digitally approximated parabola.