Abstract: The process of linearly interpolating between data taken from adjacent storage locations in a memory non-integrally addressed has the initial subtraction and final addition steps eliminated from it, and the partial products to be summed in the intervening multiplication process are modified to compensate for the elimination of these steps. This modification is done with a relatively fast select-one-of-four process, reducing the time for linear interpolation to that required for a simple multiplication--or, in the case of a single-bit multiplier, to the time for selection of the modified multiplicand to be used as linear interpolation result.