Abstract: A process for the formation of a cap layer for semiconductors with a low degree of contamination wherein the cap layer is easily formed on the surface of a semiconductor, and binding force thereof with the surface of the semiconductor is strong and stabilized, besides only the cap layer is selectively removed easily, comprises the steps of introducing nitrogen atom into a surface of a semiconductor; combining a component element of the semiconductor in the vicinity of the surface of the semiconductor into which the nitrogen atom has been introduced with the nitrogen atom to form a nitride compound being a compound of the component element of the semiconductor and the nitrogen atom; and utilizing the nitride compound as a cap layer for the surface of the semiconductor.

Abstract: A semiconductor device manufactured by cleaning without dissolving W, Ti, or TiN even if these metallic materials are exposed on the substrates to be cleaned, and a method for manufacturing such a semiconductor device. Impurities present on a silicon substrate can be removed while controlling the etching of a tungsten film exposed on the surface of a silicon substrate, by dipping and cleaning the silicon substrate in one or a plurality of chemical solutions selected from a group consisting of HF, HCl, and NH4OH, under the condition that the surface of the silicon substrate is entirely covered with a tungsten film. After dry etching for patterning the tungsten film and the barrier metal, impurities present on a silicon substrate can be removed while controlling the etching of the tungsten film and the barrier metal exposed on the surface of a silicon substrate, by dipping and cleaning the silicon substrate in one or a plurality of chemical solutions selected from a group consisting of HCl and NH4OH.

Abstract: A method for forming a conductive contact of a semiconductor device is provided. According to one aspect of the present invention, a dummy dielectric layer pattern having a dummy opening and an interdielectric layer pattern having a lower etch-rate than that of the dummy dielectric layer, for filling the dummy opening are formed on a semiconductor substrate. The dummy dielectric layer pattern using the interdielectric layer pattern as an etching mask is selectively removed, and a contact opening for exposing the semiconductor substrate of a portion in which the dummy dielectric layer pattern is located.

Abstract: A method for opening resist in raised areas of a semiconductor device, in accordance with the present invention, includes forming a conductive layer over a channel insulator layer to form a raised portion which includes a height above a substantially planar surrounding area. The channel insulator layer is aligned to a gate electrode. A photoresist layer is formed over the raised portion and the surrounding area and the photoresist is patterned by employing a gray scale light mask to reduce exposure light on the photoresist on the conductive layer over the raised portion such that after developing the photoresist, the photoresist is removed over a top surface of the raised portion but remains in the surrounding area. The conductive layer is etched in accordance with the photoresist to form source and drain electrodes which are self aligned to the channel insulator layer.

Abstract: The process consists in depositing, by chemical vapour deposition using a mixture of silicon and germanium precursor gases, a single-crystal layer of silicon or germanium on a germanium or silicon substrate by decreasing or increasing the temperature in the range 800-450° C. and at the same time by increasing the Si/Ge or Ge/Si weight ratio from 0 to 100% in the precursor gas mixture, respectively.

Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched.

Abstract: A silicon on insulator (SOI) dynamic random access memory (DRAM) cell, array and method of manufacture. The memory cell includes a vertical access transistor above a trench storage capacitor in a layered wafer. A buried oxide (BOX) layer formed in a silicon wafer isolates an SOI layer from a silicon substrate. Deep trenches are etched through the upper surface SOI layer, the BOX layer and into the substrate. Each trench capacitor is formed in the substrate and, the access transistor is formed on a sidewall of the SOI layer. Recesses are formed in the BOX layer at the SOI layer. A polysilicon strap recessed in the BOX layer connects each polysilicon storage capacitor plate to a self-aligned contact at the source of the access transistor. Dopant is implanted into the wafer to define device regions. Access transistor gates are formed along the SOI layer sidewalls. Shallow trenches are formed and filled with insulating material to isolate cells from adjacent cells.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: A semiconductor dynamic quantity sensor includes a semiconductor support substrate having a specific resistance equal to or less than 3&OHgr; cm. An insulation film is provided on the support substrate and a semiconductor layer is provided on the support substrate with the insulation film interposed therebetween. The semiconductor layer has a specific resistance equal to or less than 3&OHgr; cm. A movable electrode is provided in the semiconductor layer to be displaced according to a dynamic quantity acting thereto. A fixed electrode is fixedly provided in the semiconductor layer to make a specific gap with the movable electrode and to from a capacitor with the movable electrode. The capacitor has a capacity that changes in response to displacement of the movable electrode to detect the dynamic quantity.

Abstract: The invention relates to a process for filling a multiplicity of recesses (3) formed in an exposed surface of a workpiece (1), wherein the mouths of the recesses (3) are closed by the deposition of a layer (10) and the layer is subjected to elevated temperature and pressure to force material from the layer down into the recesses. In the particular embodiments described, the elevated temperature is achieved by supplying very short thermal pulses, for example, from a light source such as a laser or a halogen light and preferably this thermal pulse is applied after the elevated pressure has been achieved.

Abstract: A method of forming a superconducting damascene interconnect structure, and the structure made thereby, the method includes forming a cavity in an interlevel dielectric; forming a barrier layer in the cavity; forming a seed layer in the cavity over the barrier layer; filling the cavity by electrodepositing a Y—Ba—Cu alloy; and annealing in oxygen flow to form a Y—Ba—Cu—O superconductor on the barrier layer. In one embodiment, the superconductor has a formula YBa2Cu3O7-x, wherein x≦0.5. In another embodiment, the method includes forming a cavity in an interlevel dielectric; forming a Y—Ba—Cu alloy layer in the cavity; forming a seed layer in the cavity over the Y—Ba—Cu alloy layer; filling the cavity by electrodepositing a Y—Ba—Cu alloy fill; and annealing in oxygen flow to form a Y—Ba—Cu—O superconductor on the dielectric.

Abstract: An integrated fuse element is capable of being programmed to high resistance in low voltage process technology. The fuse includes a stack of an undoped polysilicon layer and a silicide layer. A voltage applied across the stack is increases until a first agglomeration event occurs, whereby a discontinuity is formed in the silicide layer. The current is further increased to cause a second agglomeration event whereby the size of the discontinuity is increased. Each agglomeration event increases the resistance of the fuse. An extended-drain MOS transistor, capable of sustaining high voltage, is connected in series with the fuse for programming the fuse.

Abstract: In order to carry out ashing at a high efficiency without leaving any residue and also to inhibit corrosion of an underlying material of a resist and further to prevent particle contamination, a photoresist is ashed at a low temperature to be removed and a residue of the photoresist is removed at a high temperature.

Abstract: In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors.

Abstract: A solid-state image-sensing device has pn-junction sensor parts isolated corresponding to pixels by a device isolation layer. The solid-state image-sensing device includes a first-conductivity-type second semiconductor well region formed between a first-conductivity-type first semiconductor well region and the device isolation layer. When the device is operating, a depletion layer of each sensor part spreads to the first semiconductor well region, which is beneath each of the sensor parts.

Abstract: A process for forming an array of memory cells that includes forming a buried bitline region by implanting an n-type dopant in a region of a semiconductor substrate, wherein there is a severe differential change going from the bitline region to the substrate region causing the capacitance of a junction between the bitline region and the semiconductor to be large and reducing the capacitance of the junction.

Abstract: A process for forming an integrated circuit structure wherein trenches and/or vias are formed in a predetermined pattern in a dielectric layer, lined with a barrier layer of a first electrically conductive material, and then filled with a second electrically conductive material, and the structure is then planarized to remove the first and second electrically conductive material from the upper surface of the dielectric layer, wherein the improvements comprise: a) before the planarizing step, forming over the second electrically conductive material a layer of a planarizable material capable of being planarized at about the same rate as the first electrically conductive material; and b) then planarizing the structure to remove: i) the planarizable material; ii) the second electrically conductive material; and iii) the first electrically conductive material; above the upper surface of the dielectric material; whereby the planarizable material above the second electrically conductive material in the trenche

Abstract: Semiconductor devices that include mismatched lattice crystal interfaces are produced by edge growth heteroepitaxy from a crystal with a small surface area to decrease crystal mismatch strain, achieving a crystal with reduced displacement faults. Mismatched crystal lattices are also deposited on a deformable thin membrane of semiconductor material to reduce strain in growing crystal and to reduce displacement faults to achieve a monolithic crystal structure.

Abstract: A method of forming a photovoltaic element according to the present invention comprises at least the steps of depositing a metal layer on a supporting member, depositing a metal oxide layer on the above metal layer, and arranging at least one or more pin structures, each of which is formed by stacking the predetermined n-type, i-type and p-type semiconductor layers, on a substrate formed by stacking on the above supporting member, the above metal layer and the above metal oxide layer in this order, wherein a step of subjecting the supporting member having the metal layer formed thereon to heat treatment is carried out between the two steps of depositing the above metal layer and depositing the above metal oxide layer.

Abstract: A fabrication method of the present invention includes the following steps: A step of forming gate electrodes in a logic circuit region; a step of forming first and second protective insulating layers in the logic circuit region; a step of forming a first gate insulating layer and a word gate layer in a memory region; a step of forming a second gate insulating layer on a semiconductor substrate and forming side insulating layers on both sides of the word gate layer in the memory region; a step of anisotropically etching the second conductive layer, thereby forming control gates in the shape of sidewalls and a conductive layer continuous with the control gates in regions in which common contact sections are formed; a step of removing the first and second protective insulating layers; and a step of forming impurity layers which form either a source or drain.