Abstract: A method of gettering layer for improving chemical mechanical polishing process in flash-memory production is provided to protect a memory element against baking and keep its reliability by blockading mobile electrons with the gettering layer. Moreover, by taking advantage of the gettering layer, reduction of the thickness of the ILD for increasing the etching margin, the deposition margin, and the remaining margin of oxides are made possible.

Abstract: An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point. The present invention also relates to assemblies comprising one or more of these substrates.

Abstract: A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum amount of capacitance per semiconductor die area.

Abstract: In a semiconductor wafer-processing, hydrogen gas is introduced into the same chamber as used for film formation and heated to generate hydrogen radicals. Alternatively, a plasma is applied to generate hydrogen radicals, or the semiconductor wafer is heated immediately before film formation. Thereby, contaminants on the surface of the wafer are removed. Thereafter, a conductive film or an insulating film is formed on the wafer in the same chamber.

Abstract: The reliability of in-laid metallization patterns, e.g., of copper or copper alloy, is significantly enhanced by voidlessly filling recesses in a substrate by an electroplating process, wherein “pinching-off” of the recess opening due to formation of overhanging metal deposits as a result of increased rate of electrodeposition thereat is prevented. Embodiments include preliminarily selectively rendering the recess opening surface non-conductive. The inventive method also enables a reduction in electrodeposition over non-recessed areas, thereby reducing the time required for planarization, as by CMP.

Abstract: Etching openings are provided in a membrane above an etched-out cavity, only at a distance of at most one tenth of the diameter of the member away from the edge of the cavity. For production, a poly layer is applied to a sacrificial layer composed of SiO2 and is provided with rows of etching holes, through which channels are etched out in the sacrificial layer. The poly layer is oxidized and is made smooth by means of a planarization layer. Etching holes are produced in the edge region of the membrane layer. The sacrificial layer is removed over the entire area of the cavity which is to be produced, with the etching medium propagating sufficiently quickly through the channels.

Abstract: A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. An N-well is formed within a silicon semiconductor substrate. A P+ region is implanted within a portion of the N-well and an N+ region is implanted within a portion of the semiconductor substrate not occupied by the N-well. An oxide layer is formed overlying the semiconductor substrate and patterned to form openings to the semiconductor substrate. An epitaxial silicon layer is grown within the openings and overlying the oxide layer. Shallow trench isolation regions are formed within the epitaxial silicon layer extending to the underlying oxide layer. Gate electrodes and associated source and drain regions are formed in and on the epitaxial silicon layer between the shallow trench isolation regions. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions.

Abstract: A semiconductor device including a structure having an upper surface and an contact surface formed at the upper surface of the structure. An insulating material is formed over the contact surface and a conductive runner extends over the active area such that a lower surface of the conductive runner is above and separated from the active area. A widened portion is formed in the conductive runner with an opening formed in the widened portion and self-aligned to edges of the widened portion. A conductive pillar is self-aligned to the opening and extends downward through the opening, through the insulating material, to the active area. The conductive runner provides local interconnection that can be routed over device features formed in and on the structure without using an additional metal layer.

Abstract: A new process to control the electrical conductivity of gallium nitride layers grown on a sapphire substrate has been developed. This process is based on initially coating the sapphire substrate with a thin layer of aluminum nitride, then depositing the gallium nitride thereon. This process allows one to controllably produce gallium nitride layers with resistivity varying over as much as 10 orders of magnitude, without requiring the introduction and activation of suitable dopants.

Abstract: A visible light emitting device includes a wide band gap semiconductor layer doped with one or more elements which emit light at various wavelengths based upon atomic transitions. The semiconductor preferably is GaN, InN, AIN, BN or alloys thereof doped with a lanthanide element such as Er, Pr or Tm. The light emission can be enhanced by annealing the WBGS.

Abstract: A 0.98 &mgr;m semiconductor laser of a ridge waveguide (RWG) structure includes: to be lengthen the durability of a semiconductor laser by increasing a catastrophic optical damage (COD) level, a ridge having a fixed width and length so that the strip may stop in the position of 30 &mgr;m on the basic of end portion of an output facet along length direction of a resonator; and a non-waveguide region in the end portion of both sides of a resonator.

Abstract: A method of fabricating a dynamic threshold voltage metal oxide semiconductor (DTMOS) for operation at threshold voltages less than 0.6 volts includes preparing a silicon substrate to form a trench in an active area; forming a silicon layer in the trench; doping the silicon layer in the trench to form a highly doped layer, having a doping ion concentration in a range of between about 5.0·1017 cm−3 and 5.0·1018 cm−3; depositing a silicon layer over the high doped silicon layer; and completing the structure to form a DTMOS transistor.

Abstract: A method of forming a triple N well is described. A first pattern mask layer is formed on a substrate. A first ion implantation step is performed to form an annular longitudinal deep N well in the substrate. A second ion implantation step is performed to form an annular longitudinal shallow N well in the substrate. The annular longitudinal shallow N well lies above the annular longitudinal deep N well. The first mask layer is removed. A second patterned mask layer is formed on the substrate. A third ion implantation step is performed to form a transversal deep N well surrounded by the annular longitudinal deep N well. The transversal deep N well is connected with the annular longitudinal deep N well. Thus a triple N well is formed. A fourth ion implantation step is performed to form a cell well surrounded by the annular longitudinal deep N well. The cell well lies above the transversal deep N well. The second mask layer is removed.

Abstract: A semiconductor device includes a polysilicon diode layer formed so that pn junctions are positioned only in a portion (first portion) of the polysilicon diode layer which overlies at least one guard ring having a field alleviating structure for holding the breakdown voltage of an IGBT, thereby to prevent the deterioration of the breakdown voltage of the polysilicon diode resulting from the operation of a MOSFET including the pn junctions of the polysilicon diode layer between the collector and gate of the IGBT, an n− drift layer and a field oxide film.

Abstract: A semiconductor package including a universal substrate with interior pads, peripheral pads, and substrate traces positioned between the interior pads and the peripheral pads. The interior pads are configured for electrical interface with a first semiconductor chip. The peripheral pads are configured for electrical interface with a second semiconductor chip that is larger than the first semiconductor chip. By providing a universal substrate that can accommodate multiple die sizes, package design time and costs can thus be reduced.

Abstract: A method for forming a platen useful for forming nanoscale wires for device applications comprises: (a) providing a substrate having a major surface; (b) forming a plurality of alternating layers of two dissimilar materials on the substrate to form a stack having a major surface parallel to that of the substrate; (c) cleaving the stack normal to its major surface to expose the plurality of alternating layers; and (d) etching the exposed plurality of alternating layers to a chosen depth using an etchant that etches one material at a different rate than the other material to thereby provide the surface with extensive strips of indentations and form the platen useful for molding masters for nano-imprinting technology. The pattern of the platen is then imprinted into a substrate comprising a softer material to form a negative of the pattern, which is then used in further processing to form nanowires.

Abstract: At least a one conductivity type nanostructure PS layer whose thickness is controlled, and the opposite conductivity type nanostructure PS layer and a one conductivity type mesostructure PS layer arranged in contact with both these sides are comprised. Since the one conductivity type nanostructure PS layer is formed by anodizing the non-degenerate n-type crystalline silicon layer whose thickness is established in advance, the thickness which can provides a maximum luminescence efficiency can be obtained correctly. Then a semiconductor light emitting device whose luminescence efficiency is improved without increasing an unnecessary series resistance is provided. An inexpensive semiconductor light emitting device having a large light emitting area can be provided, since silicon wafer having a large diameter can be employed as the material for light emission.

Abstract: Disclosed herein is a method for forming an embedded metal wiring comprising the steps of: forming a wiring trench, a barrier metal film and a conductive metal film; exposing the barrier metal film by polishing the conductive metal film by use of a polishing liquid and an oxidizing agent having a first concentration; and forming a wiring by polishing and removing the exposed barrier metal film by use of a polishing liquid and an oxidizing agent having a second concentration lower than the first concentration. The excessive polishing of the conductive metal occurs when an oxidizing agent having a relatively large concentration while such an oxidizing agent is needed when the barrier metal film is polished and removed. In order to attain the smooth removal of the barrier metal film and to prevent the excessive removal of the conductive metal, the oxidizing agent having a lower concentration is employed in the polishing of the conductive metal.

Abstract: A method of plasma doping substrates is provided. The substrate is covered with photoresist and placed within a plasma chamber. A doping gas is introduced into the chamber and ionized. A dilutant gas is also introduced to provide better control of the total amount of dosage associated with a given duration of exposure. The dilutant gas is preferably monatomic to reduce, or eliminate, affects associated with pressure variations within the chamber caused by dissociation of elements within the plasma chamber. The dilutant gas preferably contains lighter elements so as to reduce, or eliminate, damage to the photoresist caused by ion impacts. The dilutant gas is preferably neon or helium. The present method provides a means to better control the dosage and reduce photoresist damage and contamination.

Abstract: The present invention provides a process for effectively producing a high performance light emitting device. A substrate on which an N-type semiconductor layer, a light emitting layer, and a P-type semiconductor layer are formed is provided. The N-type semiconductor layer is cut to be discontinuous. Then the substrate is microwaved. Not only the present invention takes advantage of microwaving process for producing a high performance light emitting device, but also avoids the shortcoming of the device cracking due to over activation of the N-type semiconductor layer by microwave processing.