Abstract: In an embodiment, a processor includes a first chip of a multi-chip package (MCP). The first chip includes at least one core and first chip temperature control (TC) logic to assert a first power adjustment signal at a second chip of the MCP responsive to an indication that a first chip temperature of the first chip exceeds a first threshold. The processor also includes a conduit that includes a bi-directional pin to couple the first chip to the second chip within the MCP. The conduit is to transport the first power adjustment signal from the first chip to the second chip and the first power adjustment signal is to cause an adjustment of a second chip power consumption of the second chip. Other embodiments are described and claimed.

Abstract: A high-speed, low-latency configurable digital interface for a voltage regulator includes a first hardwired unit, a second hardwired unit and a programmable microcontroller interfaced between the first and second hardwired units. The first hardwired unit is operable to deserialize incoming frames received over the configurable digital interface into commands and data associated with operation of a switching voltage regulator, and serialize outgoing data into new frames for transmission over the configurable digital interface. The second hardwired unit is operable to process the commands included in the incoming frames deserialized by the first hardwired unit, and provide the outgoing data to be serialized into new frames by the first hardwired unit. The programmable microcontroller is operable to change one or more of the commands and data flowing between the first and second hardwired units.

Abstract: The present invention relates to an information processing apparatus including a power supply part and a voltage compensating circuit. The power supply part is configured to supply electric power to a first electronic device and a second electronic device. The voltage compensating circuit is configured, when the first electronic device is connected to the information processing apparatus, to increase a voltage output from the power supply part and to switch a power supply path for supplying the output voltage to the second electronic device from a first power supply path to a second power supply path including a step-down element so as to decrease the increased output voltage and to supply the decreased output voltage to the second electronic device.

Abstract: A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate multiple of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate a single processing core of the plurality of processing cores to be the bootstrap processor.

Abstract: A multi-core microprocessor supports a plurality of operating states that provide different levels of performance and power consumption to the microprocessor and its cores. A control unit puts selected cores into selected operating states at selected times. A core-specific synchronization register is provided for each core external to the core and readable by the control unit. Each core responds to an instruction to target an operating state by writing a value identifying the target operating state to the synchronization register. The control unit causes power saving actions that affect shared resources provided that the actions do not reduce performance of any core sharing the resources below the core's target operating state.

Abstract: Various techniques are provided to detect abnormal clock rates in devices such as imaging sensor devices (e.g., infrared and/or visible light imaging devices). In one example, a device may include a clock rate detection circuit that may be readily integrated as part of the device to provide effective detection of an abnormal clock rate. The device may include a ramp generator, a counter, and/or other components which may already be implemented as part of the device. The ramp generator may generate a ramp signal independent of a clock signal provided to the device, while the counter may increment or decrement a count value in response to the clock signal. The device may include a comparator adapted to select a current count value of the counter when the ramp signal reaches a reference signal. A processor of the device may be adapted to determine whether the clock signal is operating in an acceptable frequency range, based on the selected count value.

Abstract: Disclosed is a PLC system having a plurality of CPU modules and a control method thereof, wherein the method includes ascertaining a clock signal when a count is a count corresponding to a time slot allocated by a master CPU module, generating a clock signal by accessing to a backplane, and ending generation of clock signal at a time when the access to the backplane ends.

Abstract: In an embodiment, a processor includes at least one core, a first domain to operate at a first clock frequency, and a second domain to operate at a second clock frequency that is lower than the first clock frequency. The processor also includes phase locked loop (PLL) logic to generate a first signal having a first frequency corresponding to the first clock frequency and to provide the first signal to the first domain. The processor also includes a first clock to produce a first squash signal that is determined based at least in part on the second clock frequency, and also first logic to generate a second signal having a second frequency corresponding to the second clock frequency by gating the first signal with the first squash signal and to provide the second signal to the second domain. Other embodiments are described and claimed.

Abstract: A frequency calibration method applied to a Universal Serial Bus (USB) device includes: coupling the USB device to a USB host, wherein the USB device at least comprises a programmable oscillator; utilizing the USB device to extract a low frequency periodic signal from the USB host; and calibrating the programmable oscillator of the USB device according to the low frequency periodic signal, to make the programmable oscillator generate an oscillating signal having a predetermined frequency.

Abstract: Within a communication system that includes multiple communication channels, a low-power mode of operation and a higher-power mode of operation are provided. Each channel is allocated to one of several groups, based on criteria such as whether power is allocated to that channel in low power mode, and whether power was allocated to that channel in a previous high power mode. Initial power levels for each channel for each mode are approximated using an interpolation rule known to both the receive and the transmitter. The system switches between modes according to a PMD pre-defined schedule. When a new power mode begins, the receiver measures signal power received on each channel and then transmits corrective information sufficient to allow adaptation of power levels to achieve PMD pre-defined levels of received power.

Abstract: The configuration and maintenance of a computer system in a cluster, where the computer system is configured to allow booting from data stored in an administration computer system is disclosed. In one aspect, after obtaining a boot disk image making it possible to boot an operating system and configuration data from the administration computer system, the operating system is booted and configured and a virtual storage disk is created. The configuration data received are analyzed in order to obtain and store in the virtual disk a program for the configuration of the computer system. The program for the configuration of the computer system is then executed.

Abstract: A midspan power over Ethernet (“PoE”) injector (20) connects via LAN cables (514) to remote PDs (518). Each cable (514) has a remote end; and a midspan end (516). The cables (514) includes receiving and transmitting conductors, and insulated electrical conductors. The injector (20) includes pairs of sockets (24) a first socket (24) of each pair is a powered socket, and a second socket (24) is unpowered and carries only data. A data-signal bus (188) interconnects the unpowered and powered sockets. Power switches (156), equal in number to the socket pairs, connect respectively to one of the powered sockets (24). Without negotiating with a PD (518) connected by the cable (514) to the powered socket (24), a controller (34) causes switches (156) to close thereby transmitting electrical power via the powered socket (24) connected thereto and the cable (514) mated therewith to the PD (518). The controller (34) also concurrently monitors operational status: a. of each connected PD (518); and b.

Abstract: A boot recovery system includes a serial peripheral interface (SPI) storage that stores a primary boot block. A primary SPI controller is connected to the SPI storage through a primary SPI bus. An embedded controller (EC) includes an EC storage that stores a recovery boot block. The EC is coupled to the primary SPI bus through a secondary SPI bus. The EC is configured to determine that the primary boot block should be replaced, retrieve the recovery boot block from the EC storage, replace the primary boot block in the SPI storage with the recovery boot block through the secondary SPI bus, and initiate an information handling system (IHS) reboot process. The determining, retrieving, replacing, and initiating may be performed by the EC while a processing system that is coupled to the primary SPI controller is not in an operating mode.

Abstract: Methods, systems, and apparatuses can be operable to facilitate transitioning an node to and from a power-saving mode. A mixed network comprising devices having different protocols and/or specifications can communicate with each other and outdated or legacy devices can utilize power-saving modes possessed by updated devices.

Abstract: A system includes a CPU, a serial interface, and an adaptive clock delay compensator. The adaptive clock delay compensator is configured to generate a clock signal at a first frequency, detect an edge on a data signal, and count the number of clock cycles of a counter clock to measure the delay between an edge of the clock signal and the detected edge on the data signal to produce a first delay value. The CPU is configured to convert the first delay value to a different clock domain at a second frequency to produce a converted delay value, and initiate a data transfer operation using the second frequency as a clock signal. The adaptive clock delay compensator is configured to generate a delayed clock signal at the second frequency to the serial interface that is delayed from the clock signal at the second frequency by the converted delay value.

Abstract: Systems, devices, methods, computer-readable media, techniques, and methodologies are disclosed for increasing efficiency in power management for user devices. In some embodiments, a system voltage and battery voltage of a user device may be monitored and stored. The system voltage and battery voltage may be analyzed, and a system minimum voltage threshold for a user device may be modified based on the analysis of the measurements.

Abstract: There is provided a communication apparatus. A communication unit transmits data to a communication module, which communicates with an external device, according to a clock signal, and receives data from the communication module in accordance with a timing corresponding to a timing signal generated by delaying the clock signal. An adjustment unit adjusts an amount of the delay. A control unit controls the communication unit to repeatedly perform first processing for transmitting a first command to the communication module, second processing for receiving a first response that is sent from the communication module, and third processing for transmitting a packet to the communication module according to the first response. In a predetermined mode, the control unit controls the communication unit to perform processing for transmitting data of the packet regardless of contents of the first response.

Abstract: A storage battery monitoring method receives identification information indicating a storage battery system and characteristic data of a storage battery, the characteristic data including history information which indicates charging and discharging history of the storage battery; determines, based on the received history information, a deterioration model corresponding to the storage battery from among deterioration models managed in a database, the deterioration models each indicating a relationship between a state of health and a number of charging and discharging cycles performed by the battery as indicated by the charging and discharging history; generates control data for suppressing deterioration of the storage battery at a predetermined point in time according to the corresponding deterioration model; and transmits the generated control data to cause the storage battery system to control the storage battery.

Abstract: In one embodiment, a processor includes one or more cores to execute instructions and a power controller coupled to the one or more cores. In turn, the power controller includes a control logic to receive an indication, from one or more sources, of a dynamic change to a guaranteed frequency at which at least one of the one or more cores are to operate, and to determine a final guaranteed frequency at which the processor is to operate for a next window, and to communicate the final guaranteed frequency to at least one entity. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor comprises: a first domain including a plurality of cores; a second domain including at least one graphics engine; and a power controller including a first logic to receive a first performance request from a driver of the second domain and to determine a maximum operating frequency for the first domain responsive to the first performance request. Other embodiments are described and claimed.