Abstract: A responding device has operating modes including a first mode and a second mode. The responding device includes a first responding unit and a second responding unit. The first responding unit operates during the first mode and outputs, when receiving a request, a response including information in accordance with the type of the request. The second responding unit outputs the response in place of the first responding unit during the second mode. The second responding unit includes a storage section, an information accumulation section, and a mode transition control section. The information accumulation section stores in the storage section the information included in the response output from the first responding unit during the first mode. The mode transition control section causes the responding device to transition to the second mode when a first condition and a second condition in terms of the information stored in the storage section are satisfied.

Abstract: A bus system comprises a plurality of bus modules each for performing data transfer between a master module and a slave module. A power control module controls transition to a power-saving mode of each bus module based on communication with the plurality of bus modules. The power control module comprises a plurality of control modules corresponding to the plurality of bus modules respectively. Each control module performs communication with the corresponding bus module using power control signals.

Abstract: The disclosed apparatus may include (1) a power distribution unit that distributes electric power to a network device, the power distribution unit including (A) a first set of power inputs that are compatible with a first type of power source and (B) a second set of power inputs that are compatible with a second type of power source that is different from the first type of power source, and (2) a set of power supply modules electrically coupled to the power distribution unit, each power supply module within the set of power supply modules being capable of outputting electric power to the network device upon receiving current via either the first set of power inputs or the second set of power inputs. Various other apparatuses, systems, and methods are also disclosed.

Abstract: Automated modification of configuration settings for an IC (IC) includes receiving, within a data processing system, desired data for a configuration setting of an IC, reading stored data for the configuration setting. A determination is made using the data processing system that the configuration setting is static and that the stored data differs from the desired data. Responsive to the determination, configuration data including the desired data is provided from the data processing system to the IC. At least a portion of a boot process of the IC is automatically initiated, wherein the boot process uses the configuration data.

Abstract: A power management circuit including, between a first terminal intended to be connected to an electric power generation source and a second terminal intended to be connected to a load to be powered, a linear regulator and a circuit capable of activating the linear regulator when the power supplied by said source is greater than a first threshold.

Abstract: A semiconductor device includes a fuse unit comprising an array e-fuse and suitable for generating a boot-up end signal when a boot-up operation ends, a power generation unit suitable for generating a plurality of driving voltages for the fuse unit in response to a power-up signal indicating start of the boot-up operation and a power control unit suitable for controlling the generation of the driving voltages in response to the power-up signal and the boot-up end signal.

Abstract: A frequency calibration method applicable in a Universal Serial Bus device includes: plugging the Universal Serial Bus device to a Universal Serial Bus host; using the Universal Serial Bus device to receive a polling low frequency periodic signal generated from the Universal Serial Bus host; determining a host type of the Universal Serial Bus host according to the polling low frequency periodic signal; and calibrating a programmable oscillator of the USB device according to a specific clock period corresponding to the host type, to make the programmable oscillator generate a target oscillating signal having a predetermined frequency.

Abstract: A mechanism is provided for dynamic power and thermal capping in a flash storage system. A set of measurement values are received for the flash storage system, the set of measurement values comprising one or more of a set of current (I) measurement values, a set of voltage (V) measurement values, or a set of temperature (T) measurement values. An average current (Iavg) value from the set of current (I) measurements and, responsive to the average current (Iavg) value being greater than a predetermined maximum current (Imax) value, a determination is made as to whether a rate at which erase operations are performed for the flash storage system is greater than a predetermined minimum erase rate. Responsive to the rate at which erase operations are performed for the flash storage system being greater than the predetermined minimum erase rate, the rate at which erase operations are performed for the flash storage system are decreased by a predetermined value.

Abstract: A microprocessor includes a plurality of semiconductor dies, a bus coupling the plurality of semiconductor dies, and a plurality of processing cores. A distinct subset of the processing cores is located on each of the semiconductor dies. Each die comprises a control unit configured to selectively control a respective clock signal to each of the subset of cores of the die. For each core of the subset, in response to the core writing a value to the control unit, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the control unit of the other die. Collectively all of the control units are configured to simultaneously turn on the clock signals to all of the processing cores after the clock signals have been turned off to all of the processing cores.

Abstract: The electronic device may include a RAM, a nonvolatile storage device as an MTD, and firmware that may be stored on the nonvolatile storage device. The firmware may include a kernel that is expanded onto the RAM and a root disk image as a root file system. The kernel mounts the root disk image on the nonvolatile storage device as the root file system when a boot mode of the electronic device is a normal boot mode. The kernel, when the boot mode is an update mode for updating the firmware on the nonvolatile storage device, may i) generate a RAM disk as an MTD in an area of the RAM not under management of the kernel, ii) expand the root disk image on the nonvolatile storage device into the RAM disk, and iii) mount the root disk image on the RAM disk as the root file system.

Abstract: A computing device includes a first BIOS chip and a second BIOS chip. Each of the first and second BIOS chips store a BIOS image and comprises a plurality of data blocks to store BIOS data of the BIOS image. During a booting process of the computing device, the BIOS data stored in odd data blocks of the first BIOS chip and the BIOS data stored in even data blocks of the second BIOS chip are respectively accessed and are stored in a cache of a middleware controller. A processor of the computing device accesses the BIOS data from the cache of the middleware controller during the booting process.

Abstract: A processor time synchronization apparatus and method in a data communication system which includes a plurality of processors and line interfaces. The processor time synchronization apparatus includes a first local processor configured to recognize a time difference between an external device and the system based on a time message exchanged with the external device, and synchronize time between the external device and the system, and a second local processor configured to receive time information from the first local processor that has been time-synchronized with the external device, the time information containing the time difference between the external device and the system, and synchronize the first local processor with a system's internal time using the received time information.

Abstract: Systems and methods for managing power to Non-Volatile Memory Express (NVMe) devices. In some embodiments, an Information Handling System (IHS) may include a Central Processing Unit (CPU); a Non-Volatile Memory Express (NVMe) device operably coupled to the CPU; a service processor operably coupled to the CPU and to the NVMe; and a memory operably coupled to the service processor, the memory including program instructions stored thereon that, upon execution by the service processor, cause the service processor to: receive performance data from the CPU, receive metrics data from a source other than the CPU, and control an amount of power provided to the NVMe device based, at least in part, upon the performance data and the metrics data.

Abstract: A microprocessor includes a control unit configured to selectively control a respective clock signal to each of a plurality of processing cores. Each of the processing cores is configured to separately write a value to the control unit. For each core of the plurality of processing cores, the control unit is configured to turn off the respective clock signal to the core in response to the core writing a value to the control unit. The control unit is configured to detect a condition has occurred when all of the processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the processing cores. The control unit is configured to simultaneously turn on the respective clock signal to all of the processing cores in response to detecting the condition has occurred.

Abstract: A multi-core apparatus includes cores each including an active cycle counting unit configured to store an active cycle count, and a stall cycle counting unit configured to store a stall cycle count. The multi-core apparatus further includes a job scheduler configured to determine an optimal number of cores in an active state based on state information received from each of the cores, and adjust power to maintain the optimal number of cores.