Abstract: Technologies for clearing a page of memory include a memory device configured write a value to a block of memory cells in response to an activation signal. The memory device includes a row decoder responsive to a memory address to select a row of memory cells and a column decoder responsive to the activation signal to select one or more columns of memory cells. Additionally, a write driver of the memory device is configured to write a value to global input/output lines, which are connected to the selected memory cells in response to the activation signal and regardless of data received on a data input of the write driver.

Abstract: A memory circuit includes a memory cell, a first bit line, a first bit line bar, a sense amplifier, a first switch and a second switch. The memory cell is coupled with a first bit line having a first bit line portion and a second bit line portion. The first bit line bar has a first bit line bar portion and a second bit line bar portion. The sense amplifier includes a read/write circuit configured to couple the second bit line portion to a global bit line. The first switch is coupled between the first bit line bar portion and the second bit line bar portion. The second switch is coupled between the first bit line portion and the second bit line portion.

Abstract: A fast and lean way of performing logical-to-physical address translation is presented. A logical address is divided into a most significant bits portion and a least significant bits portion. Instead of using the entire logical address to locate an entry in an address translation table, only the most significant bits portion of the logical address is used, which substantially reduces the size of the address translation table. The entry includes a most significant bits portion of a physical volatile memory address and a most significant bits portion of a physical non-volatile memory address. The actual physical volatile memory address and the actual physical non-volatile memory address can be derived by combining the most significant bits portions of the addresses stored in the address translation table entry with the least significant bits portion of the logical address.

Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes a semiconductor memory, and the semiconductor memory may include a substrate; a plurality of structures formed over the substrate to be spaced apart from each other, each structure comprising a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer; and a magnetic correction layer formed adjacent to the plurality of structures and structured to reduce an influence to the free layer by a stray magnetic field generated by the pinned layer.

Abstract: The present invention relates to magnetic random access memory (MRAM) storage devices based on multiferroic tunnel junctions in which ferroelectric polarization is used to control and manipulate the memory state. Invention methods include: (1) method of producing tunneling electroresistance (TER) effect in multiferroic tunnel junction (MFTJ) at finite bias; (2) method of controlling the TER effect in an MFTJ at infinite bias via the switching of the relative orientation of the ferromagnetic leads; (3) method of producing monotonous bias dependence of the tunneling magnetoresistance (TMR) in a MFTJ; (4) method of controlling the size and direction of the parallel spin transfer torque (STT) component and the perpendicular STT component across the MFTJ; (5) method of producing a monotonous bias dependence of the perpendicular STT component across an MFTJ; and (6) method of controlling the size and sign of the interlayer exchange coupling in an MFTJ.

Abstract: Methods and apparatuses are contemplated herein for enhancing the program performance of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of nonvolatile memory cells including a plurality of layers, each layer comprising NAND strings of nonvolatile memory cells, the NAND strings coupled to a bit line, and a plurality SSLs and word lines, the SSLs and the word lines arranged orthogonally to the NAND strings, the word lines establishing the nonvolatile memory cells at cross-points between surfaces of the plurality of NAND strings and the word lines, each of the NAND strings further comprising a plurality of SSL transistors coupling the SSLs to the NAND strings, wherein at least a first SSL being configured to receive a first voltage and a second SSL configured to receive at second voltage, and wherein the second SSL being nearer to the word lines.

Abstract: A storage system includes a host configured to transmit a write command and store write data in a buffer thereof, and a storage device. The storage device includes a nonvolatile memory including a plurality of blocks, each of the blocks including a plurality of sectors and each of the sectors logically divided into at least a lower page and an upper page for data storage, and a controller configured carry out a write operation to write the write data in the nonvolatile memory in response to the write command, and return a notice to the host acknowledging that the write operation is successful. When a portion of the write data are written in a lower page of a sector of a block and an upper page of the sector remains unwritten after the write operation, the host maintains the portion of the write data in the buffer even after receiving the notice.

Abstract: After charging or discharging is stopped, a reference timing (t0) is set, and a first timing (t1) at which battery voltage (V) changes by a unit amount (N) with respect to the reference timing (t0), and a second timing (t2) at which the battery voltage changes by twice more than the unit amount with respect to the reference timing (t0) are select and set. The ratio of the time difference (t2?t1) between the first and the second timing to the time difference (t1?t0) between the reference and the first timing is found as a voltage change parameter (R) corresponding to the rate of change of the change speed of the voltage battery. An estimation device considers the change rate determined by the parameter is considered to be unchanged during an electrical current non-passage, and estimates a stable open circuit voltage at an object timing in future after the second timing.

Abstract: A life prediction apparatus for an electrical storage device, which has a life predictor, includes: an operation controller for life prediction that controls operation of the electrical storage device; a data collector that collects measurement data with respect to a plurality of operation conditions and calculates and successively accumulates evaluation characteristics; a data analyzer that creates a regression formula representing a relationship between the evaluation characteristic and an operation time by curve fitting, with an appropriate approximation function, the accumulated evaluation characteristic data; and a life prediction formula creator that creates a life prediction formula for calculating a predicted value of the evaluation characteristic under random operation conditions on the basis of the regression formula.

Abstract: An electronic device includes a semiconductor memory unit. The semiconductor memory unit may include a cell array suitable for including a plurality of resistive memory cells which are arranged in a plurality of column lines and a plurality of rows lines, and a read circuit. The read circuit is suitable for, in a read operation, generating a bias current based on bias information, supplying the bias current to a sensing node, supplying a read current from the sensing node to a column line selected from among the plurality of column lines, and sensing data stored in a selected memory cell coupled to the selected column line using a voltage level at the sensing node. The bias information is determined and stored in the semiconductor memory unit before the read operation starts.

Abstract: A method for memory management includes streaming bits to a memory buffer on a memory device using a write data channel that optimizes a speed of writing to the memory devices. The bits are written to non-volatile memory cells in the memory device at a first speed, using a bi-directional bus. Bits are read from the memory device over a read channel to provide reads at a second speed that is slower than the first speed, using the bi-directional bus.

Abstract: A test mode circuit of a semiconductor device includes a test mode activating signal generation unit suitable for generating a test mode activating signal in response to a test signal; a test clock generation unit suitable for generating a plurality of test clocks in response to the test mode activating signal and a control clock; a test control signal generation unit suitable for generating test control signals based on the plurality of test clocks of a control signal input cycle, wherein the plurality of test clocks have the control signal input cycle and a data input cycle; and an internal control signal generation unit suitable for generating a plurality of control signals to perform a test operation in response to the test control signals and input data.

Abstract: Examples are given for techniques for entry to a lower power state for a memory device or die. The examples to include delaying transitions of the memory device or die from a first higher consuming power state to a second relatively lower power state using one or more programmable counters maintained at or with the memory device.

Abstract: Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

Abstract: A nonvolatile memory device may include a memory cell array, an address decoder circuit, a page buffer circuit, and a control logic circuit. An erase operation includes iteratively performing an erase loop which includes an erase section where an erase voltage is applied to the memory cells of the selected memory block and an erase verification section where the memory cells of the selected memory block are verified using an erase verification voltage. If the memory cells of the selected memory block are determined as an erase pass in the erase verification section, the control logic circuit monitors the memory cells of the selected memory block. If the monitored result indicates that the memory cells of the selected memory block are at an abnormal state, the control logic circuit applies an extra erase voltage to the memory cells of the selected memory block.

Abstract: A write-protection system and method for use with a gaming machine. The system having a non-volatile data storage device, an interface device and an electrically conductive connector. The storage device having electronic data storage and a write-protection controller providing a write-protected state and a write-permitting state, the electronic data storage being blocked from receiving electronic write commands in the write-protected state and being able to receive write commands in the write-permitting state. The interface device electrically connecting the data storage device to a power supply and control circuitry of the gaming machine. The interface device connected to the electronic data storage through the controller and the connector.

Abstract: A memory system may include a memory device including 0th to N-1th memory blocks, wherein N is a positive integer; and a controller having a first list and a second list, wherein the first list includes 0th to N-1th erase count values respectively for the 0th to N-1th memory blocks, wherein the second list includes 0th to N-1th difference values respectively for the 0th to N-1th memory blocks, wherein each of the 0th to N-1th difference values is a difference between an average value of the 0th to N-1th erase count values and each of the 0th to N-1th erase count values, wherein the controller selects a source block and a target block among the 0th to N-1th memory blocks depending on the 0th to N-1th erase count values included in the first list and the 0th to N-1th difference values included in the second list to perform a wear leveling between the source block and the target block.

Abstract: A method of operating a memory circuit (FIGS. 8A and 8B) is disclosed. The method includes writing true data (01) to a plurality of bits (B0, B1). A first data state (0) is written to a signal bit (Bi) indicating the true data. The true data is read and complementary data (10) is written to the plurality of bits. A second data state (1) is written to the signal bit indicating the complementary data.

Abstract: According to one embodiment, a resistance change memory includes a memory cell, a reference voltage generating circuit, a first transistor and a sense amplifier. The memory cell includes a resistance change element. The reference voltage generating circuit generates a reference adjustment voltage. The first transistor provides a reference current in accordance with the reference adjustment voltage. The sense amplifier compares a cell current flowing through the memory cell with the reference current flowing through the first transistor.

Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.