Abstract: A method of forming a magnetic memory device on a substrate includes forming the memory device on a transparent substrate coated with a decomposable material layer subject to rapid heating resulting in a predetermined high pressure, transferring the memory device to the substrate, and forming an organic transistor on the substrate prior to transfer of the magnetic memory device.

Abstract: An active device array substrate including a substrate, a plurality of active devices, a plurality of the first lead lines, a plurality of the second lead lines and a first floating light-shielding layer is provided. The substrate has a display region and a peripheral circuit region and the active devices are arranged within the peripheral circuit region on the substrate to form an array. Besides, the first lead lines and the second lead lines are disposed within the peripheral circuit region on the substrate. The first floating light-shielding layer is disposed between the first lead lines and covers the part of the first lead lines. Furthermore, the floating light-shielding layer is not connected with any voltage sources completely. Therefore, the active devices array substrate can prevent the light leakage from been resulted between the first lead lines and the power consumption of the active devices array substrate is reduced.

Abstract: To improve the reliability of contact with an anisotropic conductive film in a semiconductor device such as a liquid crystal display panel, a terminal portion (182) of a connecting wiring (183) on an active matrix substrate is electrically connected to an FPC (191) by an anisotropic conductive film (195). The connecting wiring (183) is manufactured in the same process with a source/drain wiring of a TFT on the active matrix substrate, and is made of a lamination film of a metallic film and a transparent conductive film. In the connecting portion with the anisotropic conductive film (195), a side surface of the connecting wiring (183) is covered with a protecting film (173) made of an insulating material.

Abstract: A light emitting module for generating a light includes a semiconductor light emitting unit for generating a light, a plurality of nanophosphor particles having diameters which are smaller than a half-wavelength of the light generated from the light emitting module and serving to emit a fluorescent light corresponding to the light generated from the semiconductor light emitting unit, and a binder for holding the nanophosphor particles like a layer covering a light emitting surface of the semiconductor light emitting unit. Furthermore, a lighting unit for a vehicle includes the light emitting module.

Abstract: This method for optimizing the performance of a semiconductor detector intended to detect electromagnetic radiation, especially X-rays or ? rays, equipped with electrodes separately mounted on two opposite surfaces of said detector, namely a cathode and a pixelated anode respectively, involves (i) determining the signal that is representative of the sum of the charges detected by all or some of the anodes; and (ii) using the signal that is representative of said sum of the charges to establish one or more biparametric spectra as a function of this signal so as to determine any charge collection loss if charge sharing occurred on the pixelated anodes and, consequently, performing appropriate processing depending on the type of result desired.

Abstract: A system and method are provided for qualifying or calibrating lithographic apparatus or parts therefor, using a predetermined objective criterion such as Chauvenet's criterion is used to reject measurement points, individually, by field or by substrate.

Abstract: Etching is performed on an insulating layer 23 and a conductive layer 32 with a photoresist 41 as the mask, to form an opening 51 in the conductive layer 32. After removing the photoresist 41, another insulating layer 24 is formed all over, which is etched back so as to expose a surface of a conductive layer 31, to thereby cover the inner wall of the opening 51. Then etching is performed on the conductive layer 31 with the latter insulating layer 24 as the mask, so as to form another opening 52 in the conductive layer 31. Then still another insulating layer 25 is formed all over, which is then etched back so as to expose a surface of the conductive layer 32, to thereby fill the opening 52 with the last formed insulating layer 25.

Abstract: A semiconductor device in the form of a resin sealed semiconductor package is disclosed, wherein a gate terminal connected to a gate pad electrode formed on a surface of a semiconductor chip and a source terminal connected to a source pad electrode formed on the chip surface exposed to a back surface of a sealing resin portion, a first portion of a drain terminal connected to a back-surface drain electrode of the semiconductor chip is exposed to an upper surface of the sealing resin portion, and a second portion of the drain terminal formed integrally with the first portion of the drain terminal is exposed to the back surface of the sealing resin portion.

Abstract: A semiconductor device may be manufactured by a method that includes forming an etch stop layer on a semiconductor substrate, sequentially forming a first interlayer insulating layer, a first diffusion barrier, a second interlayer insulating layer, and a second diffusion barrier on the etch stop layer, forming a via hole exposing the etch stop layer by etching the second diffusion barrier, the second interlayer insulating layer, the first diffusion barrier, and the first interlayer insulating layer, forming a first trench overlapping the via hole by etching the second diffusion barrier and the second interlayer insulating layer, forming a second trench continuous to the first trench by etching the first diffusion barrier and part of the first interlayer insulating layer, and removing the etch stop layer exposed through the via hole, wherein the first and second trenches are etched under different dry etching conditions.

Abstract: A bolometer type ultra-sensitive silicon sensor pixel of a multi-pixel sensor wherein each pixel includes a detector stage, an intermediate stage, and a heat bath stage. The detector stage, the intermediate stage and a portion of the heat bath stage are generally co-planar and are interconnected by I-beam bridges so as to permit mutually co-planar rotation in response to stress and strain. Electrical coupling is improved between a micro-antenna and the detector stage by a two stage transformer assembly that couples the micro-antenna to the detector stage.

Abstract: The present invention relates generally to neutron detecting scintillators and related methods and devices. A neutron detecting scintillator includes a plurality of microcapillary tubes loaded with a scintillator composition comprising a plastic scintillator and a neutron absorbing material. The present invention additionally provides methods of producing a neutron detecting scintillator having a plurality of microcapillary tubes loaded with a scintillator composition comprising a plastic scintillator and a neutron absorbing material. The method includes preparing a solution comprising a monomer and a neutron absorbing element, introducing the solution into a microcapillary tube of the plurality, and polymerizing the solution within the microcapillary tube.

Abstract: Alignment methods of IC device substrates. A first IC device substrate has a first front side for defining a plurality of first IC features, a first backside opposite the first front side, and a first alignment pattern formed on the first front side or the first backside. A second IC device substrate has a second front side for defining a plurality of second IC features, a second backside opposite the second front side, and a second alignment pattern formed on the second front side or the second backside. A first optical detector and a second optical detector are applied to detect the first and second alignment patterns, so as to align the first and second IC device substrates. Specifically, the first and second alignment patterns face toward the first and second optical detectors in opposite directions.

Abstract: In a method for forming a gate in a semiconductor device, a first preliminary gate structure is formed on a substrate. The first preliminary gate structure includes a gate oxide layer, a polysilicon layer pattern and a tungsten layer pattern sequentially stacked on the substrate. A primary oxidation process is performed using oxygen radicals at a first temperature for adjusting a thickness of the gate oxide layer to form a second preliminary gate structure having tungsten oxide. The tungsten oxide is reduced to a tungsten material using a gas containing hydrogen to form a gate structure. The tungsten oxide may not be formed on the gate structure so that generation of the whiskers may be suppressed. Thus, a short between adjacent wirings may not be generated.

Abstract: The MEMS Sensor Suite on a Chip provides the capability, monolithically integrated onto one MEMS chip, to sense temperature, humidity, and two axes of acceleration. The device incorporates a MEMS accelerometer, a MEMS humidity sensor, and a MEMS temperature sensor on one chip. These individual devices incorporate proof masses, suspensions, humidity sensitive capacitors, and temperature sensitive resistors (thermistors) all fabricated in a common fabrication process that allows them to be integrated onto one micromachined chip. The device can be fabricated in a simple micromachining process that allows its size to be miniaturized for embedded and portable applications. During operation, the sensor suite chip monitors temperature levels, humidity levels, and acceleration levels in two axes. External circuitry allows sensor readout, range selection, and signal processing.

Abstract: A method for fabricating a semiconductor device is provided. The method includes: implanting impurities onto a substrate by performing an ion implantation process; recessing portions of the substrate to form a plurality of trenches; performing a first thermal process to form junction regions between the trenches in the substrate by diffusing the impurities and simultaneously to form a gate oxide layer on the substrate and on the junction regions; forming a polysilicon layer on the gate oxide layer; sequentially etching the polysilicon layer and the gate oxide layer to form a gate structure, and to form first spacers on lateral walls of the junction regions; forming second spacers on lateral walls of the first spacers and the gate structure; and forming a metal silicide layer on top portions of the junction regions and the gate structure.

Abstract: A method for determining a location of IR-cut filter film on a substrate, the filter film and the substrate cooperatively functioning as an IR-cut filter, includes the steps of: providing an infrared laser device, an IR-cut filter and an infrared laser sensor; emitting a laser from the IR laser device to a surface of the IR-cut filter in a manner such that the laser beam is obliquely incident on an edge portion of the IR-cut filter; and determining the location of the filter film on the substrate of the IR-cut filter in such a way that, if the intensity of the laser beam received by the infrared sensor is equal to or close to zero, the location of the filter film is on a surface of the substrate facing towards the infrared laser device; if the intensity of the laser beam received by the infrared sensor is the same as or close to an intensity of the laser beam emitted from the infrared laser device, the location of the filter film is on a surface of the substrate facing away from the infrared sensor.

Abstract: A method of fabricating a germanium photo detector includes preparing a silicon substrate wafer and depositing and planarizing a silicon oxide layer on the silicon substrate. Contact holes are formed in the silicon oxide layer. An N+ epitaxial germanium layer is grown on the silicon oxide layer and in the contact holes. An N+ germanium layer is formed by ELO. The structure is smoothed and thinned. An intrinsic germanium layer is grown on the N+ epitaxial germanium layer. A P+ germanium layer is formed on the intrinsic germanium layer and a silicon oxide overcoat is deposited. A window is opened through the silicon oxide overcoat to the P+ germanium layer. A layer of conductive material is deposited on the silicon oxide overcoat and in the windows therein. The conductive material is etched to form individual sensing elements.

Abstract: A method of producing a relief structure on a patterned conductor comprises the steps of; coating a layer of conductive material onto a transparent substrate, coating a layer of metal onto the layer of conductive material, coating a layer of photoresist onto the layer of metal, curing the layer of photoresist, exposing a desired pattern of transparent conductors through a first mask onto the layer of photoresist, developing the photoresist and simultaneously etching the layer of the conductive material and the layer of metal, exposing a desired pattern of metal conductors through a second mask onto the remaining layer of photoresist, developing the photoresist and etching the layer of metal, applying a further layer of photoresist, curing the further layer of photoresist, exposing the further layer of photoresist thorough the substrate, developing the photoresist and allowing the layer to dry, resulting in a pattern of spacers/reliefs in registration with the metal conductors.

Abstract: The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystalline layer, and in particular aspects an entirety of the active region within the crystalline layer is within a single crystal of the crystalline layer. The SRAM constructions can be formed in semiconductor on insulator assemblies, and such assemblies can be supported by a diverse range of substrates, including, for example, glass, semiconductor substrates, metal, insulative materials, and plastics. The invention also includes electronic systems comprising SRAM constructions.

Abstract: A method for manufacturing a semiconductor device includes expanding an active region and a recess region by an epitaxial growth process. As a result, a margin is sufficiently secured in processes for forming a device isolation film that defines the active region and for expanding a recess region to form a bulb recess region.