Abstract: A semiconductor device includes a first memory cell having a substrate, an insulation layer disposed over the substrate, a first polysilicon gate formed over the insulation layer, at least one oxide spacer formed contiguous with one vertical sidewall of the first polysilicon gate, a silicide formed over a horizontal surface of the first polysilicon gate, a first phase change layer formed over a portion of the silicide, contiguous with the oxide spacer, and over a portion of the insulation layer, and a first diffused region formed in the substrate. The first phase change layer is formed above the first diffused region. A second diffused region is formed spaced-apart from the first diffused region in the substrate.

Abstract: The invention provides a display device (26) including a plurality of discrete display segments (2). Each display segment (2) is provided with a drive circuit for driving the display elements arranged within the display area. The display device may be provided either as a passive, active or direct pixel addressed array. By interconnecting a number of display segments, a large area display can be achieved without the requirement for long electrodes. This reduces the electrical resistance and parasitic capacitance of the addressing electrodes, enabling the display to provide improved luminance in a displayed image and to operate at higher speeds, providing improved resolution. An active matrix addressing scheme can also be implemented using relatively low mobility organic thin film transistors.

Abstract: A semiconductor device comprises: a first main electrode; a second main electrode; a semiconductor base region of a first conductivity type; a gate electrode provided in a trench through an insulating film, the trench being formed to penetrate the semiconductor base region; and a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type provided under the semiconductor base region. A flow of a current between the first and second main electrodes when a voltage of a predetermined direction is applied between these electrodes is controllable in accordance with a voltage applied to the gate electrode. A depleted region extends from a junction between the first and the second semiconductor regions reaching the trench.

Abstract: A lead frame for making a semiconductor package is disclosed. The leadframe's leads include a lead lock provided at a free end of each inner lead that is adapted to increase a bonding force of the inner lead to a resin encapsulate, thereby effectively preventing a separation of the inner lead from occurring in a singulation process involved in the fabrication of the semiconductor package. A semiconductor package fabricated using the lead frame and a fabrication method for the semiconductor package are also disclosed.

Abstract: A microelectronic package is made by a process which includes folding a substrate. Alignment elements on different parts of the substrate engage one another during the folding process to position the parts of the substrate precisely relative to one another. One or more of the alignment elements may be a mass of an overmolding encapsulant covering a chip.

Abstract: A semiconductor component includes a chip on board leadframe, a semiconductor die back bonded and wire bonded to the leadframe, an encapsulant on the die and an area array of terminal contacts on the leadframe. The leadframe includes leadfingers, interconnect bonding sites for wire bonding the die, terminal bonding sites for the terminal contacts, and bus bars which electrically connect selected leadfingers to one another. The interconnect bonding sites are located on the leadframe relative to the bus bars such that shorting to the bus bars by wire interconnects is eliminated. A method for fabricating the component includes the steps of attaching the die to the leadframe, bonding the wire interconnects to the die and to the interconnect bonding sites, forming the encapsulant, and then forming the terminal contacts on the terminal bonding sites.

Abstract: A barrier layer made of AlxGa1?xN (0<x?0.18) is formed in a light-emitting semiconductor device using gallium nitride compound having a multi quantum-well (MQW) structure. By controlling a composition ratio x of aluminum (Al) or thickness of the barrier layer, luminous intensity of the device is improved. An n-cladding layer made of AlxGa1?xN (0<x?0.06) is formed in a light-emitting semiconductor device using gallium nitride compound. By controlling a composition ratio x of aluminum or thickness of the n-cladding layer, luminous intensity of the device is improved. A p-type layer and an n-type layer are formed in a light-emitting semiconductor device using gallium nitride compound having a double-hetero junction structure. By controlling a ratio of a hole concentration of the p-type layer and an electron concentration of the n-type layer approximates to 1, luminous intensity of the device is improved.

Abstract: The semiconductor elements for the small signal type circuits and the Au wire for connection are integrated as one package to produce the semiconductor devices 30A, 31A, 32, 33A, 34A and 38. In this way, the wire bonding of Au can be omitted, and the wire bonding of the small diameter Al wire and the large diameter Al wire is only required to complete the connection of the fine metal wire. These semiconductor devices have a plurality of circuit elements as one package, so that the mounting operation on the mounting board can be significantly reduced.

Abstract: A method and structure for a photodiode array comprising a plurality of photodiode cores, light sensing sidewalls along an exterior of the cores, logic circuitry above the cores, trenches separating the cores, and a transparent material in the trenches is disclosed. With the invention, the sidewalls are perpendicular to the surface of the photodiode that receives incident light. The light sensing sidewalls comprise a junction region that causes electron transfer when struck with light. The sidewalls comprise four vertical sidewalls around each island core. The logic circuitry blocks light from the core so light is primarily only sensed by the sidewalls.

Abstract: Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

Abstract: A versatile structure is formed, based on a deep trench, vertical transistor DRAM cell, that forms a conductive extension of the trench electrode in an elongated trench that contacts the lower electrode of the vertical transistor. The structure can be used as a capacitor, as a discrete transistor as a single-transistor amplifier or as a building block for more complex circuits.

Abstract: Disclosed is a noise shield type multi-layered substrate which is advantageous in terms of shielding leaked magnetic flux and cross-talk by disposing a magnetic material onto at least one of circuit patterns, passive components and active components, thus blocking noise generated from the circuit patterns, passive components and active components. Thus, malfunctions of neighboring circuit patterns and various parts due to leaked magnetic flux are prevented. A method of manufacturing the noise shield type multi-layered substrate is also provided.

Abstract: The present invention provides a flexible printed circuit which is free from curl, torsion and warpage due to temperature change and excellent flexural endurance. By using polyimide film having an average coefficient of thermal expansion of 1.0×10?5 to 2.5×10?5 cm/cm/° C. in a temperature range of 100° C. to 200° C. and a stiffness value of 0.4 to 1.2 g/cm as the base film for the flexible printed circuit, a flexible printed circuit having excellent thermal dimensional stability and flexural endurance can be prepared.

Abstract: A non-volatile memory device is provided by forming a tunnel oxide layer and a gate electrode on the tunnel oxide layer. Silicon structures are formed below the side surfaces of the gate electrode and act as a floating gate electrode for the non-volatile memory device.

Abstract: A metamorphic device including a substrate structure upon which a semiconductor device can be formed. In the metamorphic device, a buffer layer matching a substrate lattice constant is formed at normal growth temperatures and a thin grading layer which grades past the desired lattice constant is configured at a low temperature. A reverse grading layer grades the lattice constant back to match a desired lattice constant. Thereafter, a thick layer is formed thereon, based on the desired lattice constant. Annealing can then occur to isolate dislocated material in at least the grading layer and the reverse grading layer. Thereon a strained layer superlattice is created upon which a high-speed photodiode or other semiconductor device can be formed.

Abstract: A bumped wafer for use in making a chip device. The bumped wafer includes two titanium layers sputtered alternatingly with two copper layers over a non-passivated die. The bumped wafer further includes under bump material under solder bumps contained thereon.

Abstract: A manufacturing method of a semiconductor device comprises the steps of forming an etching stop insulating film (18) that covers at least side surfaces of a wiring (16) in a first region (2) and a first-stage conductive plug (15b) in a second region (3), then forming insulating films (20, 28) on the etching stop insulating film (18) and the wiring (16), then forming a hole (28) on a first-stage conductive plug (15b) by etching a part of the insulating films (20, 28) until the etching stop insulating film (18) is exposed, then exposing an upper surface of the first-stage conductive plug (15b) by etching selectively the etching stop insulating film (18) through the hole (28), and then forming a second-stage conductive plug (31a) in the hole (28).

Abstract: Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

Abstract: Semiconductor device includes a pair of substrates (1, 2) disposed oppositely, semiconductor elements (5, 6) formed in the substrates (1, 2), respectively, and having semiconductor circuits (3, 4) and electrodes (7, 8), respectively, a wiring conductor (9) interposed between the electrodes (7, 8), and a through electrode (12) extending through one substrate (1) and connected to the electrode (7) via the wiring conductor (9). The other substrate (2) is disposed laterally of the through electrode (12). Surface of the through electrode (12) projecting from the one substrate (1) and lateral surface of the element (6) are coated with an insulation material (13). The through electrode (12) has one end exposed in a back surface of the one substrate (1), while other end is positioned flush with a back surface of the other substrate (2), being exposed.

Abstract: The invention includes semiconductor constructions. In one implementation, semiconductor construction includes a first conductive material. A first layer of a dielectric material is over the first conductive material. A second layer of the dielectric material is on the first layer. A second conductive material is over the second layer of the dielectric material. A construction in accordance with an implementation of the invention can include a pair of capacitor electrodes having capacitor dielectric material therebetween comprising a composite of two immediately juxtaposed and contacting, yet discrete, layers of the same capacitor dielectric material.