Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Different sets of power delivery trigger circuits may be coupled to the integrated circuit by wiring or serial communication interfaces. Power reduction responses may be implemented at faster rates utilizing the wired power delivery trigger circuits while slower power reduction response can be implemented utilizing serially connected power delivery trigger circuits. The threshold for power reduction response by wired power delivery trigger circuits may also be closer to a functional failure point of the integrated circuit in order to provide fast response to avoid failure of the integrated circuit.

Abstract: A method for managing information handling systems includes initiating, by a stackable system role (SSR) manager of an information handling system of the set of information handling systems, a boot sequence, making a first determination that the boot sequence does not specify a SSR of the information handling system, based on the first determination: performing a hardware evaluation to identify available hardware resources of the information handling system, obtaining a hardware resource inventory based on the available resources, applying a hardware resource function to the hardware resource inventory to determine a SSR for the information handling system, and continuing the boot sequence using the SSR.

Abstract: A source device includes a first control unit to perform a negotiation with the sink device based on power standard and perform control of supplying power to a sink device based on first power information determined by the negotiation. The source device includes a power detection unit to detect power required by the sink device and includes a second control unit to receive the first power information including voltage and current values of power determined by the negotiation and of second power information including voltage and current values of power detected. The second control unit generates third power information, including voltage and current values based on the inputs of the first power information and the second power information and on the predetermined power standard. The second control unit instructs the first control unit to perform negotiation again on the basis of the third power information generated.

Abstract: A method of peak power management (PPM) is provided for two NAND memory dies. each NAND memory die comprises a PPM circuit having a PPM contact pad held at an electric potential common between the two NAND memory dies. The method includes the following steps: detecting the electric potential during a first peak power check (PPC) routine for the first NAND memory die; driving the electric potential to a second voltage level if the detected electric potential is at a first voltage level higher than the second voltage level; generating a pausing signal in the electric potential to pause a second PPC routine for the second NAND memory die if no pausing signal is detected; and generating a resuming signal in the electric potential to resume the second PPC routine for the second NAND memory die after the first NAND memory die completes a first peak power operation.

Abstract: A power supply for a power line includes a synchronization module having a receiver configured for receiving a clock signal from a satellite-based positioning system and an oscillator configured for generating a periodic signal synchronized to the received clock signal. The power supply includes an inverter module having an inverter configured for supplying an AC voltage to the power line, receiving the periodic signal from the synchronization module, and controlling the inverter using the received periodic signal as a synchronization reference signal for the supplied AC voltage. The power supply further includes a power exchange control module configured for: monitoring an active power flow P from the inverter module to the power line, determining whether the active power flow P satisfies a reverse-flow condition, and when the reverse-flow condition is determined, adapting at least one of a phase and an output voltage of the supplied AC voltage.

Abstract: There is described a system for translating clock domain for non-synchronized sensors comprising a first sensor, a second sensor, and an upstream device. The first and second sensors receive a beacon from a tag. Each sensor transmits a report including a beacon receive time in a sensor clock domain. The upstream device receives the reports and translates beacon receive times from the sensor clock domain to an aggregator clock domain. The translation is based, at least in part, on beacon reception data of the sensors, report transmission data of the sensors, and report reception data of the upstream device. The upstream device determines a location of the tag based on a delta of the beacon receive times in the aggregator clock domain.

Abstract: An electronic system has a plurality of processing clusters including a first processing cluster. The first processing cluster further includes a plurality of processors and a power management processor. The power management processor obtains performance information about the plurality of processors, executes power instructions to transition a first processor of the plurality of processors from a first performance state to a second performance state different from the first performance state, and executes one or more debug instructions to perform debugging of a respective processor of the plurality of processors. The power instructions are executed in accordance with the obtained performance information and independently of respective performance states of other processors in the plurality of processors of the first processing cluster.

Abstract: A storage apparatus includes a control chip, a storage chip, a power interface configured to receive a first voltage, a first variable-voltage circuit. An input end of the first variable-voltage circuit is coupled to the power interface. The first variable-voltage circuit is configured to convert the first voltage into a second voltage, and provide the second voltage to the control chip and a second variable-voltage circuit, where an input end of the second variable-voltage circuit is coupled to the power interface. The second variable-voltage circuit is configured to convert the first voltage into a third voltage and provide the third voltage to the control chip and the storage chip.

Abstract: System and methods may include receiving a request for assigning resources to a first application associated with a first entity, the first application having a plurality of levels of performance each corresponding to a different power consumption; and determining a particular level of performance of the first application to run on the resource under a first constraint that a sum of a power consumption of the first application running at the particular level of performance and power consumptions of one or more other resources running other applications associated with the first entity is less than or equal to a power budget associated with the first entity.

Abstract: Data is identified that defines a known good state for a current operating system. The identified data includes read-only sets that are not updated during operation of the computing device, and modifiable sets that can be updated during operation of the computing device. The read-only sets are captured on an opportunistic basis and the modifiable sets are captured when the computing device is to be rebooted. A first and second virtual disk are allocated as snapshots of the identified data. The first virtual disk is updated to generate an updated state. The updates to the first virtual disk are isolated from the second virtual disk. The second virtual disk is maintained as an immutable snapshot of the identified data. In response to a failed reboot with the updated state, the computing device reverts to the known good state using the snapshot of the identified data.

Abstract: A method for controlling at least one setting of a basic input output system (BIOS) of at least one automated transaction machine (ATM) can include provisioning features of an active management technology system of a first computing device associated with an ATM. The method can also include establishing an initial trust between the first computing device and a second computing device that is remote from the first computing device, over a serial-over-lan (SOL) connection that is a feature of the active management technology system. The method can also include configuring the setting of the BIOS of the first computing device and storing a schedule for changing the setting of the BIOS. The method can also include reconfiguring the setting of the BIOS in response to the schedule stored on the database over the SOL.

Abstract: A sensing apparatuses includes a sensor, a processing circuit that acquires sensor output information from the sensor, a communication circuit that transmits transmission information corresponding to the sensor output information, and a clocking circuit that generates time information. The communication circuit receives time information for correction before the processing circuit starts acquiring the sensor output information. The clocking circuit corrects the time information based on the time information for correction received by the communication circuit. The processing circuit starts acquiring the sensor output information based on the corrected time information.

Abstract: A rated power supply system powered by PoE receives power from external power sources and supplies power to PDs. The system connects with PDs through PoE output interfaces. The system has a PoE analog controller to turn on/off of the output power of all the PoE output interfaces. The PoE analog controller also detects the output current of all the PoE output interfaces. The system has a packet switch controller, a power state detecting circuit and a voltage conversion circuit. The voltage conversion circuit merges the power received from external power sources to generate a first voltage. The CPU calculates an output current upper limit based on the first voltage. The CPU gets a total output current from the PoE analog controller. If the total output current exceeds the output current upper limit, the CPU will turn off the PoE output interfaces according to power output priorities of the PoE output interfaces.

Abstract: A sensor device coupled to a communication interface bus, the sensor device enters a low power mode in which some operations of the sensor device are suspended when the sensor device receives insufficient power over the bus, thereby significantly reducing the likelihood that digital components of the sensor device will need to be reset due to an under-voltage condition.

Abstract: A power consumption estimation method is provided, which is performed by a power consumption control device including a correlation database that stores data indicating a correlation between an operation state and power consumption of at least one household information communication device. The power consumption estimation method includes an operation state information acquisition step of acquiring operation state information from each household information communication device, a power consumption acquisition step of acquiring power consumption of each household information communication device by referring to the correlation database by using the operation state information, and a presenting step of presenting power consumption information by function for the at least one household information communication device, based on the power consumption of each household information communication device.

Abstract: A method for controlling at least one setting of a basic input output system (BIOS) of at least one automated transaction machine (ATM) can include provisioning features of an active management technology system of a first computing device associated with an ATM. The method can also include establishing an initial trust between the first computing device and a second computing device that is remote from the first computing device, over a serial-over-lan (SOL) connection that is a feature of the active management technology system. The method can also include configuring the setting of the BIOS of the first computing device and storing a schedule for changing the setting of the BIOS. The method can also include reconfiguring the setting of the BIOS in response to the schedule stored on the database over the SOL.

Abstract: Embodiments disclosed herein describe systems and methods for tuning phases of interface clocks of ASICs in an emulation system for a low latency channel and to avoid read errors. During a bring-up time (e.g., powering up) of the emulation system, one or more training processors may execute a software application to iteratively tune the phases of the interface clocks such that data is written to the interface buffers prior to being read out. To mitigate the problem of higher latency, the training processors may execute software application to tune the clock phases such that there is a small time lag between the writes and reads. The training processors may set the time lag to account for factors such as memory setup and hold, clock skews, clock jitters, and the predicted margin required to account for future clock drift due to carrying operating conditions.

Abstract: A plurality of messages can be received from a remote device, each of the messages including a respective sent time from the remote device. A receiver can store a respective receipt time of each of the messages. A computer clock can be adjusted based on a first difference between respective sent times and a second difference between respective receipt times.

Abstract: A method of peak power management (PPM) is provided for two NAND memory dies. Each NAND memory die comprises a PPM circuit having a PPM contact pad held at an electric potential common between the two NAND memory dies. The method includes the following steps: detecting the electric potential during a first peak power check (PPC) routine for the first NAND memory die; driving the electric potential to a second voltage level if the detected electric potential is at a first voltage level higher than the second voltage level; generating a pausing signal in the electric potential to pause a second PPC routine for the second NAND memory die if no pausing signal is detected; and generating a resuming signal in the electric potential to resume the second PPC routine for the second NAND memory die after the first NAND memory die completes a first peak power operation.

Abstract: There is provided a method of controlling performance boosting of a semiconductor device. According to the method, input of a user is monitored. A performance of the semiconductor device is boosted by consecutively executing a plurality of boosting policies associated with a plurality of macros based on an input event associated with the input of the user and available energy during a boosting interval. Boosting level in each of the boosting policies may be adaptively determined based on the boosting level and the amount of usage of the semiconductor device used in the previous boosting policy and the boosting policies are consecutively executed. Accordingly, improved and/or optimal performance boosting can be provided to the semiconductor device and at the same time, a waste of power can be mitigated and/or prevented.