Abstract: Efficient buffer cache utilization frees a data buffer as soon as data buffer processing is completed, and without losing association of the freed data buffer and a descriptor buffer. Separate free buffer link lists identify the freed data buffer and any freed descriptor buffer. The data buffer is rapidly processed then freed generally before completion of processing of the descriptor buffer, freeing the processed associated data buffer before the associated descriptor buffer is freed. The association of the processed free data buffer and the descriptor buffer may be ended to enable the more frequent use of the large capacity data buffer for other update requests.

Abstract: Short-quasi-unique-identifiers (SQUIDs) are generated and assigned to the data objects stored in memory. Pointers to a particular data object contain the data object's assigned SQUID. If a data object is moved to a second allocated memory segment, a new pointer to the second allocated memory segment is placed at the original memory segment, so that any pointers to the original memory segment now point to the new pointer. The distribution of SQUIDs is uniform. SQUIDs can be generated by counting, generated randomly, generating through some hashing mechanism, or other means. In comparing two different pointers, it is determined that the two pointers do not reference the same data object if the SQUIDs are different. On the other hand, if the SQUIDs are identical and the address fields of the two pointers are identical, then the two pointers reference the same data object.

Abstract: The present invention provides a method as well as an architecture for a host equipped with a CPU-level processing capability to access a Non-Volatile Random Access Memory (NVRAM) and at least a controller via a simple 3-wire/4-wire mechanism. The data stored in the NVRAM are shared with the controller and the host. More importantly, a multi-access mechanism further having a pragmatic bit determines the pragmatic bit for either the controller or the NVRAM. With the method of the present invention, computer system resources can be fully utilized, and thereby, peripheral devices can be easily added to the system in an inexpensive and highly efficient way.

Abstract: A data processing system and a data processor in which the control information for controlling an external device, especially, a device having a PCMCIA interface is stored in an address translation circuit for translating a first address outputted from a CPU to a second address in association with the first or second address.

Abstract: Drives of a data storage library are concurrently configured. A processor transmits library configuration data separately to each drive, initializes a first configuration process state, with a time-out period, for each drive. A drive responds with a status response, the first process state is updated to “completed”. A request for drive unique information is transmitted to the responding drive, advancing the process to a second state, with a time-out period. A drive responds with the information, and the second process state is updated to “completed”, and the received information is stored.

Abstract: Apparatus and methods to adaptively throttle accesses to memory employ a masking tool to specify the percentage of memory bandwidth available for access. The apparatus applies the mask and monitors the number of memory accesses during a throttle-monitoring window. If the number of memory accesses during the throttle-monitoring window exceeds or is fewer than the percentage of memory bandwidth specified by the mask, access to the memory continues until the end of the throttle-monitoring window. At the end of the throttle-monitoring window, the apparatus selects the next lower mask, which has a lower memory bandwidth allocation, applies the next lower mask, and monitors the number of memory accesses during the next throttle-monitoring window.

Abstract: A method of internally executing an externally initiated access to a dynamic memory array including a plurality of dynamic memory cells, wherein the dynamic memory cells require periodic refreshing, is achieved. The method comprises, first, determining if an external access to the dynamic memory array has been initiated. Second, a waiting period of RW idle time is inserted. The RW idle time comprises a sum of a row access time plus a pre-charge time. A pending refresh is performed during said RW idle time. A pending write access may be performed during the RW idle time. Finally, the external access is internally executed in the dynamic memory array after the RW idle time.

Abstract: Descriptored information is stored in a file system according to a Uniform Disk Format Specification UDF. It accommodates storage of both data and descriptor items, through separating a descriptor item from the data through storing the former in a dedicated logical sector. In particular, the descriptor items are assigned to a dedicated and immediately accessible directory space. Within the directory space, successive logical sectors are mapped at mutual stepping distances that are a factor less than a physical sector size that is uniform among data and descriptor items.

Abstract: A data storage system having a plurality of disk drives. Each one has a pair of bi-directional ports. A pair of directors controls the flow of data to and from the disk drives. A first fiber channel port by-pass selector section is provided. The first fiber channel by-pass selector section includes: an input/output port coupled to a first one of the directors; and, a plurality of output/input ports connected between a first one of the ports of the plurality of disk drives through a first plurality of fiber channel links. The first fiber channel port by-pass selector section is adapted to couple the first one of the directors serially to one, or ones, of the first ports of the plurality of disk drives through a first fiber channel selectively in accordance with a control signal fed to the first fiber channel by-pass selector section. The first fiber channel includes one, or more, of the first plurality of fiber channel links.

Abstract: A method, system, program, and data structure for restricting host access to at least one logical device. Each logical device comprises a section of physical storage space that is non-overlapping with the physical storage space associated with other logical devices. At least one logical device and at least one host are assigned to a cluster group. A cluster group is defined such that hosts that are not in a particular cluster group cannot access the logical devices that are assigned to the cluster group. Further, within each cluster group, a logical number is assigned to each logical device in the cluster group such that no host member of that cluster group uses the assigned logical number to access another logical device. The hosts in the cluster group use the logical number to access the logical device to which the logical number is assigned.

Abstract: A heap is a memory resource managed in units of cells and it is used in units of cells by the execution of an application program. A full garbage collection unit collects free cells based on the check result of the state of use of cells. A partial garbage collection unit collects free cells from cells that are used after the check of the state of use of cells recently made by the full garbage collection unit, based on the check result of the state of use of cells. A full/partial control unit improves the process efficiency of parallel type garbage collection by making either the full garbage collection unit or the partial garbage collection unit perform a subsequent collection of free cells based on the state of collections made in the past.

Abstract: The invention relates to a circuit arrangement and to a method for creating and retrieving replacement data. The circuit arrangement has a programmed ROM, which is coupled to a patch-memory module through an address and data bus. The patch-memory module has a plurality of patch-data registers and patch-address registers, in which the addresses and replacement data are stored. The invention makes it possible that a hard-wired and thus irreversibly programmed ROM can be modified and corrected by an external circuit arrangement. For example, erroneous instructions of program sequences and data can be replaced by error correction instructions during a ROM access of the program-controlled unit. By using dedicated registers, the RAM essentially can be dispensed with for error correction, while retaining the retrieval speed.

Abstract: The invention relates to cache apparatuses and a control method for managing cache memories in a multiprocessor system. A cache controller holds data which has to be invalidated for a cache coherence as data in a status where the validity is unknown, causes a cache hit in response to a reading request from a processor, provides the data as speculation data, and allows the processor to speculatively process the data. Therefore, since the data which has to be obtained from another cache or a main storage due to the invalidation is held in an Unknown status, a cache hit occurs. Thus, a data waiting time of the processor can be shortened.

Abstract: The present invention discloses a method and system for streaming an information stream from a producer to N consumers in a multi-process environment. An inter-process communication (IPC) channel containing a shared memory is provided between the producer and at least one of N consumers. The information stream is written into the shared memory by way of a producer-side interface. The information stream is read from the shared memory by way of a consumer-side interface.

Abstract: A data processing apparatus is embodied in a single integrated circuit. The data processing apparatus includes a central processing unit, at least one level one cache, a level two unified cache and a directly addressable memory. The at least one level one cache preferably includes a level one instruction cache temporarily storing program instructions for execution by the central processing unit and a level one data cache temporarily storing data for manipulation by said central processing unit. The level two unified cache and the directly addressable memory are preferably embodied in a single memory selectively configurable as a part level two unified cache and a part directly addressable memory. The single integrated circuit data processing apparatus further includes a direct memory access unit connected to the directly addressable memory and adapted for connection to an external memory. The direct memory access unit controls data transfer between the directly addressable memory and the external memory.

Abstract: A cache controller is disclosed that includes a first means for determining when data specified by a memory address requested by the processor is absent from the cache, and a second means for determining when the processor reads sequential memory addresses. The second means is activated when the first means detects that data is absent from the cache and causes the cache controller to (i) permit data to be supplied from the main memory to the processor, even when the data is available in the cache; (ii) inhibit the first means from determining whether requested data is available in the cache; and (iii) update the cache with data supplied to the processor from the main memory.

Abstract: A programmable agent and method for managing prefetch queues provide dynamically configurable handling of priorities in a prefetching subsystem for providing look-ahead memory loads in a computer system. When it's queues are at capacity an agent handling prefetches from memory either ignores new requests, forces the new requests to retry or cancels a pending request in order to perform the new request. The behavior can be adjusted under program control by programming a register, or the control may be coupled to a load pattern analyzer. In addition, the behavior with respect to new requests can be set to different types depending on a phase of a pending request.

Abstract: The present invention provides fault contained memory partitioning in a cache coherent, symmetric shared memory multiprocessor system while enabling fault contained cache coherence domains as well as cache coherent inter partition memory regions. The entire system may be executed as a single coherence domain regardless of partitioning, and the general memory access and cache coherency traffic are distinguished. All memory access is intercepted and processed by the memory controller. Before data is read from or written to memory, the address is verified and the executed operation is aborted if the address is outside the memory regions assigned to the processor in use. Inter cache requests are allowed to pass, though concurrently the accessed memory address is verified in the same manner as the memory requests.

Abstract: A method and apparatus for efficiently managing caches with non-power-of-two congruence classes allows for increasing the number of congruence classes in a cache when not enough area is available to double the cache size. One or more congruence classes within the cache have their associative sets split so that a number of congruence classes are created with reduced associativity. The management method and apparatus allow access to the congruence classes without introducing any additional cycles of delay or complex logic.

Abstract: Provided are a system, method, program, and data structure for processing a request for data in a first format that is superimposed on blocks of data stored in a second format in a storage device. A data structure for a storage unit in the first format including the requested data is accessed. There is one data structure for each storage unit in the first format being accessed. Further, at least one cache page storing blocks of data in the second format is needed to store one storage unit in the first format. A determination is made of one or more storage blocks in the second format that include the requested data. A determination is also made as to whether the storage unit data structure includes a pointer to a control block for a cache page that would include the determined storage blocks in the second format.