Abstract: A partitioned cache and management method for selectively caching data by type improves the efficiency of a cache memory by partitioning congruence class sets for storage of particular data types such as operating system routines and data used by those routines. By placing values for associated applications into different partitions in the cache, values can be kept simultaneously available in cache with no interference that would cause deallocation of some values in favor of newly loaded values. Additionally, placing data from unrelated applications in the same partition can be performed to allow the cache to rollover values that are not needed simultaneously.

Abstract: A method and apparatus automatically and easily verifies a cache line prefetch mechanism. The verification method includes a strict definition of which cache lines should be prefetched and which cache lines should not. The method also emphasizes unusual operating conditions. For example, by exercising boundary conditions, the method by stresses situations in which a microprocessor or chip is likely to produce errors. The method can verify prefetch without having to access or view any internal signals or buses inside the chip. The method can be adopted in any system-level verification methodology in simulation, emulation, or actual hardware. The method can be used in a system-level test set up along with a chip-level test set up without requiring knowledge of the internal state of the chip. In this case, checking is done at the chip boundary. The method is automated and performs strict checks on overprefetch, underprefetch, and the relative order in which fetch and prefetches must occur.

Abstract: A least recently used (LRU) cache replacement algorithm is implemented with a set of N pointer registers that point to respective ways of an N-way set of memory blocks. One of the pointer registers is an LRU pointer, pointing to a least recently used way and another of the pointer registers is a most recently used (MRU) pointer, pointing to a most recently used way. For a cache fill operation in which a new memory block is written to one of the N ways, the new memory block is written into the way (wayn), pointed to by the LRU pointer. All the pointers except the MRU pointer are promoted to point to a way pointed to by respective newer neighboring pointers, the newer neighboring pointers being neighbors towards the MRU pointer. The MRU pointer is updated to point to the wayn in which the new memory block was written.

Abstract: Speculative pre-fetching and pre-flushing of additional cache lines minimize cache miss latency and coherency check latency of an out of order instruction execution processor. A pre-fetch/pre-flush slot (DPRESLOT) is provided in a memory queue (MQUEUE) of the out-of-order execution processor. The DPRESLOT monitors the transactions between a system interface, e.g., the system bus, and an address reorder buffer slot (ARBSLOT) and/or between the system interface and a cache coherency check slot (CCCSLOT). When a cache miss is detected, the DPRESLOT causes one or more cache lines in addition to the data line, which caused the current cache miss, to be pre-fetched from the memory hierarchy into the cache memory (DCACHE) in anticipation that the additional data would be required in the near future.

Abstract: Two banks of memory are selectively accessed from a first interface terminal and a second interface terminal through multiplexer circuitry whereby one memory bank can be read by one terminal while the other memory bank is being updated from the other interface terminal. The multiplexer circuitry is controlled by a control register which responds to an operation code whereby either memory bank can be updated while the other memory bank is being read for hardware parameters, for example.

Abstract: A method and system for increasing system memory bandwidth within a symmetric multiprocessor data-processing system are disclosed. The symmetric multiprocessor data-processing system includes several processing units. With conventional systems, all these processing units are typically coupled to a system memory via an interconnect. In order to increase the bandwidth of the system memory, the system memory is first divided into multiple partial system memories, wherein an aggregate of contents within all of these partial system memories equals to the contents of the system memory. Then, each of the processing units is individually associated with one of the partial system memories, such that the bandwidth of the system memory within the symmetric multiprocessor data-processing system is increased.

Abstract: A distributed-memory multiprocessor system uses fast and main coherency directories to implement cache coherency. The main directory is stored with user data in main memory and includes sufficient information to determine which memory cells have cached copies of user data stored in main memory. In addition, the main directories specify the states of the cached data. The fast directories cache only some of the main-directory information for only a fraction of the main-memory locations at any given time. The fast directories are tagless in one mode and use partial tags in another mode. The fast-directory information is accessed concurrently with main-directory information in response to data requests. Directory information is retrieved first from the fast directory and is used to launch predictive recalls. Subsequently received main-directory information is used to validate or invalidate the predictive recalls.

Abstract: A system and method for caching objects of non-uniform size. A caching logic includes a selection logic and an admission control logic. The admission control logic determines whether an object not currently in the cache is accessed may be cached at all. The admission control logic uses an auxiliary LRU stack which contains the identities and time stamps of the objects which have been recently accessed. Thus, the memory required is relatively small. The auxiliary cache serves as a dynamic popularity list and an object may be admitted to the cache if and only if it appears on the popularity list. The selection logic selects one or more of the objects in the cache which have to be purged when a new object enters the cache. The order of removal of the objects is prioritized based both on the size as well as the frequency of access of the object and may be adjusted by a time to obsolescence factor (TTO).

Abstract: A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it can guarantee a sequential order of the ordered transaction and the next ordered transaction. This visibility indication allows the bus agent to proceed with the next ordered transaction without waiting for the completion status of the deferred transaction. The visibility indication provides fast processing of ordered transactions.