Abstract: A semiconductor device includes: a first insulating layer; a semiconductor layer provided on the first insulating layer; a first semiconductor region selectively provided in the semiconductor layer; a second semiconductor region selectively provided in the semiconductor layer and spaced from the first semiconductor region; a first main electrode provided in contact with the first semiconductor region; a second main electrode provided in contact with the second semiconductor region; a second insulating layer provided on the semiconductor layer; a first conductive material provided in the second insulating layer above a portion of the semiconductor layer located between the first semiconductor region and the second semiconductor region; and a second conductive material provided in a trench provided in a portion of the semiconductor layer opposed to the first conductive material, being in contact with the first conductive material, and reaching the first insulating layer.

Abstract: The present invention relates to a rotorcraft blade (1) provided with a distributed spar (10) on a leading edge (4), a suction side (2), and a pressure side (3) of the blade, and the invention also relates to a method of fabricating such a spar. The blade is provided with a fastener insert (20) integrated in the blade root for the purpose of fastening the blade to a rotor, the fastener insert (20) comprising a horizontal shaft (21) perpendicular to the span of the blade and to an axis of rotation of said rotor, with the distributed spar (10) of the blade being wound in part about the horizontal shaft.

Abstract: A semiconductor device includes a chip comprising a contact element, a structured dielectric layer over the chip, and a conductive element coupled to the contact element. The conductive element comprises a first portion embedded in the structured dielectric layer, a second portion at least partially spaced apart from the first portion and embedded in the structured dielectric layer, and a third portion contacting a top of the structured dielectric layer and extending at least vertically over the first portion and the second portion.

Abstract: Various embodiments include apparatus and methods having circuitry to test continuity of conductive paths coupled to dice arranged in a stack.

Abstract: The present invention relates to a light emitting diode and a method of fabricating the same, wherein the distance between a fluorescent substance and a light emitting diode chip is uniformly maintained to enhance luminous efficiency. To this end, there is provided a light emitting diode comprising at least one light emitting diode chip, lead terminals for use in applying electric power to the light emitting diode chip, and a frame that is used for mounting the light emitting diode chip thereon and is formed to have a predetermined height and a shape corresponding to that of the light emitting diode chip.

Abstract: An interconnect structure is provided. The interconnect structure includes an interconnect opening formed within a dielectric material, a diffusion barrier on the dielectric material, where the diffusion barrier contains a compound from a thermal reaction between cobalt (Co) metal from at least a portion of a cobalt metal layer formed on the dielectric material and a dielectric reactant element from the dielectric material. The interconnect structure further includes a cobalt nitride adhesion layer in the interconnect opening, and a Cu metal fill in the interconnect opening, wherein the diffusion barrier and the cobalt nitride adhesion layer surround the Cu metal fill within the interconnect opening.

Abstract: A stacked semiconductor package and a method for manufacturing the same are presented which exhibit a reduced electrical resistance and an increased junction force. The semiconductor package includes at least two semiconductor chips stacked upon each other. Each semiconductor chip has a plurality of bonding pads formed on upper surfaces and has via-holes. First wiring lines are located on the upper surfaces of the semiconductor chips, on the surfaces of the via-holes, and respectively connected onto their respective bonding pads. Second wiring lines are located on lower surfaces of the semiconductor chips and on the surfaces of the respective via-holes which connect to their respective first wiring lines. The semiconductor chips are stacked so that the first wiring lines on an upper surface of an upwardly positioned semiconductor chip are respectively joined with corresponding second wiring lines formed on a lower surface of a downwardly positioned semiconductor chip.

Abstract: An integrated circuit (IC) package includes a printed circuit board (PCB) substrate and a plurality of package attachment terminals. The package attachment terminals are used to conduct electrical signals from a die that is attached and bonded onto the PCB substrate. The PCB substrate has a side edge and includes a plurality of electrically-conductive paths. Each one of the plurality of paths includes an electroplated bond pad, a trace, and a stub trace. The die is connected to the bond pad and the trace couples the bond pad to a respective one of the package attachment terminals. The stub trace is used to facilitate the electroplating process. The stub trace extends from the trace and terminates at a distance away from the side edge. The stub trace is not visible from the side of the IC package and therefore prevents access to IC buses on the package.

Abstract: In semiconductor devices having a copper-based metallization system, bond pads for wire bonding may be formed directly on copper surfaces, which may be covered by an appropriately designed protection layer to avoid unpredictable copper corrosion during the wire bond process. A thickness of the protection layer may be selected such that bonding through the layer may be accomplished, while also ensuring a desired high degree of integrity of the copper surface.

Abstract: There is provided a semiconductor device formed of a highly integrated high-speed CMOS inverter coupling circuit using SGTs provided on at least two stages. A semiconductor device according to the present invention is formed of a CMOS inverter coupling circuit in which n (n is two or above) CMOS inverters are coupled with each other, each of the n inverters has: a pMOS SGT; an nMOS SGT, an input terminal arranged so as to connect a gate of the pMOS SGT with a gate of the nMOS SGT; an output terminal arranged to connect a drain diffusion layer of the pMOS SGT with a drain diffusion layer of the nMOS SGT in an island-shaped semiconductor lower layer; a pMOS SGT power supply wiring line arranged on a source diffusion layer of the pMOS SGT; and an nMOS SGT power supply wiring line arranged on a source diffusion layer of the NMOS SGT, and an n?1th output terminal is connected with an nth input terminal.

Abstract: A post-mold plated semiconductor device has an aluminum leadframe (105) with a structure including a chip mount pad and a plurality of lead segments without cantilevered lead portions. A semiconductor chip (210) is attached to the chip mount pad, and conductive connections (212) span from the chip to the aluminum of the lead segments. Polymeric encapsulation material (220), such as a molding compound, covers the chip, the connections, and portions of the aluminum lead segments without leaving cantilevered segment portions. Preferably by electroless plating, a zinc layer (301) and a nickel layer (302) are on those portions of the lead segments, which are not covered by the encapsulation material including the aluminum segment surfaces (at 203b) formed by the device singulation step, and a layer (303) of noble metal, preferably palladium, is on the nickel layer.

Abstract: A mounted body (100) of the present invention includes: a semiconductor element (10) having a surface (10a) on which element electrodes (12) are formed and a rear surface (10b) opposing the surface (10a); and a mounting board (30) on which wiring patterns (35) each having an electrode terminal (32) are formed. The rear surface (10b) of the semiconductor element (10) is in contact with the mounting board (30), and the element electrodes (12) of the semiconductor element (10) are connected electrically to the electrode terminals (32) of the wiring pattern (35) formed on the mounting board (30) via solder connectors (20) formed of solder particles assembled into a bridge shape. With this configuration, fine pitch connection between the element electrodes of the semiconductor element and the electrode terminals of the mounting board becomes possible.

Abstract: Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends partially through the substrate and is in contact with the bond-pad.

Abstract: A plurality of origin patterns (3) containing a metal catalyst are formed over a semiconductor substrate (1). Next, an insulating film (4) covering the origin patterns (3) is formed. Next, a trench allowing at the both ends thereof the side faces of the origin patterns (3) to expose is formed. Thereafter, a wiring is formed by allowing carbon nanotubes (5) having a conductive chirality to grow in the trench. Thereafter, an insulating film covering the carbon nanotubes (5) is formed.

Abstract: A semiconductor module (10) includes a heat sink (1), an electronic component (2), a semiconductor device (3), and a thermally-conductive sheet member (4). The thermally-conductive sheet member (4) covers a part of the semiconductor device (3) and has a lower part (4b) and a side part (4c). The lower part (4b) is in contact with a mounting face (11a) of the heat sink (1). The side part (4c) extends from the lower part (4b) and covers a first side surface (3c) of the semiconductor device (3). The electronic component (2) is disposed across the side part (4c) of the thermally-conductive sheet member (4) from the semiconductor device (3).

Abstract: The present invention provides novel compounds of the formula Gei-x-ySixSny, wherein 0.01<y<0.11, and 0.26<x<0.35, and semiconductor structures comprising such compounds. The present invention also provides novel semiconductor structures comprising silicon substrates, an SiGe buffer layer, and a Group III-V or II-VI active layer. The present invention also provides novel semiconductor structures comprising silicon substrates, an SiGe buffer layer, an SiGeSn template layer, and an SiGe, Ge, Group III-V, or Group II-VI active layer.

Abstract: A semiconductor package structure having a solder ball coupled to a chip pad and a manufacturing method thereof, a semiconductor package module, and a system. A circuit board includes a through hole therein, and a conductor is formed on a sidewall of the through hole. A first semiconductor chip including a first chip pad is mounted on the circuit board. A solder ball is disposed in the through hole and is bonded to the conductor and the first chip pad. Therefore, an underfill can be removed from a semiconductor package, and thus, the semiconductor package can be reduced in thickness.

Abstract: A phase-change nonvolatile memory (PRAM) is constituted of a semiconductor substrate, a lower electrode, a first interlayer insulating film having a first hole, an impurity diffusion layer embedded in the first hole, a second interlayer insulating film having a second hole whose diameter is smaller than the diameter of the first hole, a phase-change recording layer, and an upper electrode. The impurity diffusion layer is constituted of two semiconductor layers having different conductivity types, wherein one semiconductor layer is constituted of a base portion and a projecting portion having a heating spot in contact with the phase-change recording layer, while the other semiconductor layer is formed to surround the projecting portion. A depletion layer is formed in proximity to the junction surface so as to reduce the diameter of the heating spot, thus reducing the current value Ireset for writing data in to the phase-change recording layer.

Abstract: Each of junctions formed between a semiconductor device and a substrate comprises metal balls of Cu, or other materials and compounds of Sn and the metal balls, and the metal balls are bonded together by the compounds.

Abstract: A semiconductor package is provided and methods for bonding wires in the semiconductor package. In one implementation, the semiconductor package includes a lead frame including a first die pad and a second die pad; each die pad is supported by one or more supports and isolated from another; at least first and second dice, a first die being disposed on the first die pad and a second die being disposed on the second die pad; wire bonds in communication with the first and second dice; and an encapsulant adapted to encapsulate the die pads, the dice, the lead frame and the wire bonds.