Abstract: A semiconductor package and method of fabricating has a substrate having conductive patterns formed thereon. A semiconductor die is attached to the substrate. An electrically connecting member is electrically coupled to the semiconductor die and the conductive patterns. A plurality of lands is coupled to the substrate. At least one land is pivotally mounted to the substrate. A first section of the pivotally mounted land is in contact with the substrate. A second section of the pivotally mounted land is floating to form a void area between the substrate and the second section. An encapsulant is used for encapsulating a top surface of the substrate, the semiconductor die, and the electrically connecting member. A solder ball is electrically coupled to each land.

Abstract: A gas or an insulating material having a relative dielectric constant of not more than 2.5 on average is interposed between a first wiring layer and a second wiring layer included in a multilayer wiring structure. Between a wiring of the first wiring layer and a wiring of the second wiring layer, a conductive connector is arranged. Between a predetermined wiring of the first wiring layer and a predetermined wiring of the second wiring layer, an insulating heat conductor having a relative dielectric constant of not more than 5 is arranged.

Abstract: A chip structure comprising a silicon substrate, a MOS device, dielectric layers, a metallization structure, a passivation layer, a plurality of metal layers and a polymer layer. The metallization structure comprises a first circuit layer and a second circuit layer over the first circuit layer, and comprises a damascene electroplated copper. The passivation layer is over the metallization structure and dielectric layers, the passivation layer including a first opening exposing a contact point of the metallization structure. The polymer layer is disposed over the passivation layer and the first metal layer, a second opening in the polymer layer being over a second contact point of the first metal layer, the polymer layer covering a top surface and sidewall of the first metal layer. The second contact point is connected to the first contact point through the first opening, the second opening not being vertically over the first opening.

Abstract: Memory cells which include a semiconductor substrate having a source region and a drain region separated by a channel region; a charge-trapping structure disposed above the channel region of the semiconductor substrate; a first gate disposed above the charge-trapping structure and proximate to the source region; and a second gate disposed above the charge-trapping structure and proximate to the drain region; where the first gate and the second gate are separated by a first nanospace are provided, along with arrays including a plurality of such cells, methods of manufacturing such cells and methods of operating such cells.

Abstract: A self-aligned wafer or chip structure including a substrate, at least one first concave base, at least one second concave base, at least one connecting structure and at least one bump is provided. The substrate has a first surface and a second surface, and at least one pad is formed on the first surface. The first concave base is disposed on the first surface and electrically connected to the pad. The second concave base is disposed on the second surface. The connecting structure passes through the substrate and disposed between the first and second concave bases so as to be electrically connected to the first and second concave bases. The bump is filled in the second concave base and protrudes out of the second surface.

Abstract: A light emitting diode lamp is disclosed that includes a resin package that defines a recess in the shape of a solid polygon or another three-dimensional solid. The recess includes a floor, two side walls along the respective longer sides of the floor, and two end walls along the respective shorter sides of the floor. The two side walls define an angle therebetween greater than 3°, and the two end walls define an angle therebetween greater than 40°. A light emitting diode chip is positioned on the rectangular floor of the package.

Abstract: A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.

Abstract: The present invention is to implement a SOP of a mobile RFID interrogator. The substrate has external connection terminal patterns on a first surface of a substrate and circuit wiring patterns on a second surface of the substrate. a high frequency front-end part, a power amplifier IC, an analog-digital signal processing chip and the like are mounted on the second surface. The high frequency front-end part is to transmit and receive a RFID signal. The power amplifier IC is to output an amplified high frequency transmission signal to the high frequency front-end part. The analog-digital signal processing chip is to output a high frequency transmission signal to the power amplifier IC and process the RFID signal received through the high frequency front-end part, a mold resin is to cover the second surface and components mounted on the second surface for electrical insulation from outside and physical protection from outside.

Abstract: A light-emitting device structure comprises a substrate having a first region and a second region outside the first region, a first conductive type semiconductor layer positioned on the first region, a light-emitting structure positioned on the first conductive type semiconductor layer, a second conductive type semiconductor layer positioned on the light-emitting structure, and a wall structure positioned on the second region.

Abstract: The carrier frame relating to the present invention comprises a base layer member, a frame layer member, and a positioning layer member having multiple openings for storing electronic components. A spring layer member is mounted in a hollow part surrounded by the frame layer member between the positioning layer member and the base layer member. At each opening of the spring layer member, a small spring providing an elastic force for fastening the electronic components between an edge of the corresponding opening of the positioning layer member and the small spring is formed integrally with the spring layer member. At one end in the longitudinal direction of the spring layer member, a large spring providing an elastic force along the longitudinal direction by being in contact with an inner surface of the frame layer member in the mounted state is formed integrally with the spring layer member.

Abstract: A method for forming a device wafer with a recyclable support by providing a wafer having first and second surfaces, with at least the first surface of the wafer comprising a semiconductor material that is suitable for receiving or forming electronic devices thereon, providing a supporting substrate having upper and lower surfaces, and providing the second surface of the wafer or the upper surface of the supporting substrate with void features in an amount sufficient to enable a connecting bond therebetween to form a construct wherein the bond is formed at an interface between the wafer and the substrate and is suitable to maintain the wafer and supporting substrate in association while forming or applying electronic devices to the first surface of the wafer, but which connecting bond is severable at the interface due to the void features to separate the substrate from the wafer so that the substrate can be reused.

Abstract: Various integrated circuit devices, in particular a junction field-effect transistor (JFET), are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described.

Abstract: A light-emitting device operating on a high drive voltage and a small drive current. LEDs (1) are two-dimensionally formed on an insulating substrate (10) of e.g., sapphire monolithically and connected in series to form an LED array. Two such LED arrays are connected to electrodes (32) in inverse parallel. Air-bridge wiring (28) is formed between the LEDs (1) and between the LEDs (1) and electrodes (32). The LED arrays are arranged zigzag to form a plurality of LEDs (1) to produce a high drive voltage and a small drive current. Two LED arrays are connected in inverse parallel, and therefore an AC power supply can be used as the power supply.

Abstract: A photoelectric conversion device comprising a photo-electric conversion part including a first electrode layer, a second electrode layer and a photoelectric conversion layer provided between the first electrode layer and the second electrode layer, wherein light is made incident from an upper part of the second electrode layer into the photoelectric conversion layer; the photoelectric conversion layer generates a charge containing an electron and a hole corresponding to the incident light from the upper part of the second electrode layer; and the first electrode layer works as an electrode for extracting the hole.

Abstract: A method for forming a metal wiring of a semiconductor device capable of efficiently preventing a hillock phenomenon occurred in a subsequent annealing process of a metal wiring process. The method for forming a metal wiring of a semiconductor device includes forming an Al growth stop film on the upper interface of an Al wiring film by reacting implanted reactive ions with a Ti film or the Al in the Al wiring film.

Abstract: Structures having low-k multilayered dielectric diffusion barrier layer having at least one low-k sublayer and at least one air barrier sublayer are described herein. The multilayered dielectric diffusion barrier layer are diffusion barriers to metal and barriers to air permeation. Methods and compositions relating to the generation of the structures are also described. The advantages of utilizing these low-k multilayered dielectric diffusion barrier layer is a gain in chip performance through a reduction in capacitance between conducting metal features and an increase in reliability as the multilayered dielectric diffusion barrier layer are impermeable to air and prevent metal diffusion.

Abstract: A semiconductor includes a channel region in a semiconductor substrate, a gate dielectric film on the channel region, and a gate on the gate dielectric film. The gate includes a doped metal nitride film, formed from a nitride of a first metal and doped with a second metal which is different from the first metal, and a conductive polysilicon layer formed on the doped metal nitride film. The gate may further include a metal containing capping layer interposed between the doped metal nitride film and the conductive polysilicon layer.

Abstract: A photo sensor includes a patterned shielding conductive layer disposed on a transparent substrate, and a buffer dielectric layer, a patterned semiconductor layer, and a dielectric layer disposed on the patterned shielding layer in order. The patterned semiconductor layer includes an intrinsic region, a first doped region, and a second doped region, wherein the first and second doped regions are positioned at two sides of the intrinsic region separately. A patterned transparent conductive layer is disposed on the dielectric layer and covers the boundary of the intrinsic region and the first doped region and the boundary of the intrinsic region and the second doped region. The patterned transparent conductive layer is electrically connected to the patterned shielding conductive layer.

Abstract: A method of manufacturing an electronic component includes the steps of: a) forming via holes penetrating through a first semiconductor substrate and a second semiconductor substrate which are bonded together by way of a connection layer; b) pattern-etching the second semiconductor substrate using the connection layer as an etch-stop layer to form trenches communicated with the via holes; and c) integrally forming first via plugs buried in the via holes and pattern wirings buried in the trenches through plating.

Abstract: A conductive through connection having a body layer and a metal layer is disposed on a semiconductor device, which the metal layer is on a top of body layer and includes a conductive body configured to penetrate the body layer and the metal layer. The width/diameter of one end of the conductive body is larger than that of another end thereof. The shape of these two ends of the body layer can be rectangular or circular.