Abstract: A phase detector circuit that prevents a significant loss of lock during input of CIDs (Consecutive Identical Digits) and has a high linearity of a phase to voltage conversion characteristic around a phase-locked point in an operation of comparing phases of random NRZ signals in a phase. By using the phase detector circuit having a circuit configuration containing a delay circuit and a combination of leapt a multiplier circuit and a subtractor circuit, a capability as the PLL circuit of preventing the significant loss of lock can be realized. In addition, since a duty cycle of a pulse appearing at an output terminal 3 of a multiplier circuit 62 approaches 50% as a phase-locked state is approached, a distortion in the phase to voltage conversion characteristic does not appear, and thus high linearity of the phase to voltage conversion characteristic around thus phase-locked point can be realized.

Abstract: Various methods and circuits for implementing high speed peak amplitude comparison. The invention achieves higher speed of operation by eliminating the slow feedback loop commonly employed in peak detection. In one embodiment, the invention directly compares a signal that represents the peak amplitude of the input signal minus a small voltage drop, to a modified reference voltage. The modified reference voltage corresponds to the reference voltage that is adjusted to compensate for the small voltage drop in the maximum input voltage. In another embodiment, the invention implements a differential version of the peak amplitude comparator to obtain better noise rejection and reduced effective offset among other advantages.

Abstract: A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.

Abstract: A PLL circuit including a generating means (3) for generating a plurality of reference signals (fR1 to fR8) having mutually differing phases, a main frequency divider (30) dividing an output signal (fVCO) of a voltage-controlled oscillator (29) by a frequency-division ratio of N1, an auxiliary frequency divider (31) dividing an output (fV?) of the main frequency divider by a frequency-division ratio of N2, a distribution circuit (32) distributing an output (Q1a, Q2a, Q3a) of the auxiliary frequency divider as a plurality of feedback signals (fV1 to fV8), and phase comparators (12 to 19) comparing the reference signals with the feedback signals to output error signals (ER1 to ER8). Each of the main frequency divider and the auxiliary frequency divider is comprised of a variable frequency divider or a counter.

Abstract: Provided is system for an improved programmable gain amplifier (PGA). The system includes an amplifier and a first gain control mechanism. The first gain control mechanism includes a circuit input port and is positioned along a feedback path of the amplifier. The first gain control mechanism is configured to (i) receive an input signal and (ii) moderate gains applied to the received input signal, the applied gains including gain values of greater than or equal to one. A second gain control mechanism is coupled to the first gain control mechanism and is integrated with a function of the amplifier. The second gain control mechanism (i) provides gain values of less than one and (ii) decreases a feedback factor of the amplifier when the gain values are provided having values of less than one.

Abstract: Circuit for correcting a duty factor of a clock signal, including a phase comparator for detecting a phase difference of an input clock signal having a duty factor to be corrected, and a corrected clock signal having the duty factor corrected, and generating a shift control signal, a control signal generating part for shifting a clock generating reference signal in response to the shift control signal, and delaying the clock generating reference signal for a preset time period to generate 180° and 360° clock generating control signals, and a clock signal generating part for generating a clock signal having a corrected duty factor according to the 180° and 360° clock generating control signals.

Abstract: A monolithic LC filter which provides increased magnetic field coupling as compared with a conventional monolithic LC filter, without an increase in component size of the filter. The monolithic LC filter includes first and second resonator inductors coupled together by magnetic field coupling. The inductors include parallel-extending straight coupling sections formed by conductive lines which extend in parallel generally along a diagonal of a supporting dielectric layer. This configuration enables the lengths of the coupling sections to be increased as compared with the lengths of the corresponding coupling sections of a conventional monolithic LC filter.

Abstract: A frequency divider circuit is disclosed that generates output signals having a frequency substantially half of the frequency of the input signal. The circuit comprises two D-Flip-Flop circuits wherein one employs the said input signal and the other one employs the complement of the said input signal, and each of the two D-Flip-Flop circuits consists of a pair of loading transistors, two regenerative pairs coupled with each others, and two common-gate switches.

Abstract: A system and method of generating a clock. A first clock is accessed. A delayed version of the first clock is created. A second clock signal is generated. A first edge of the second clock signal corresponds to a transition of the first clock signal, and a second edge of the second clock signal corresponds to a transition of the delayed version of the first clock signal.

Abstract: A bang-bang phase detector circuit for use in a delay lock loop is disclosed. The phase detector includes a data signal line, a clock signal line, and a delay cell having an input coupled to the data signal line. The phase detector further includes a first double flip-flop having a data input coupled to the data signal line and a clock input coupled to the clock signal line, and a second double flip-flop having a data input coupled to an output of the delay cell and a clock input coupled to the clock signal line. A NOR circuit has a first input coupled to an output of the first double flip-flop and a second input coupled to an output of the second double flip-flop. The phase detector provides a lag output signal line coupled to an output of the NOR circuit, and a lead output signal line coupled to the output of the second double flip-flop.

Abstract: A continuous-time baseline restoration (BLR) circuit providing built-in pulse tail-cancellation, or BLR tail-cancel circuit, in constant fraction discriminator (CFD) arming and timing circuits. The BLR tail cancel circuit is applied at the output of constant fraction timing shaping filters and arming circuits to permit monolithic integrated circuit implementation of CFD circuits operating at high input signal count rates. The BLR tail-cancel circuit provides correction of dc offset and count-rate dependent baseline errors along with simultaneous tail-cancellation. Correction of dc offsets due to electronic device mismatches and count-rate dependent baseline errors is required for accurate time pickoff from the input signals. The reduction of pulse width, or pulse tail-cancellation is required to shorten the duration of high count rate signals to prevent the severe distortion caused by the occurrence a new signal superimposed on the tails of previous signals, a condition known as pulse pileup.

Abstract: A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operates in a full-drive and reduced-drive mode in response to an output drive strength bit having first and second logic states, respectively. The delay-locked loop adjusts the delay of the clock signal in response to the state of the output drive strength bit to keep the data or clock signals from the buffer synchronized during both modes of operation.

Abstract: A multi-stage integrator achieves a relatively high small-signal gain, broad bandwidth, and very clean transient pulse response. Only simple amplifying stages (typically including an inverting amplifier(s)) are used. A high gain amplifier is coupled between an integrator input node and amplifier output node. A broadband single stage amplifier (which may comprise or act as a transconductor), may act as a current source for the output transistor and load, coupled between the integrator input node and output node. Preferably, a capacitance is coupled from the integrator input to the amplifier output. A frequency-selective element or network steers signal components to the single stage amplifier or the integrator appropriately to produce a combined output that has the desired characteristics.

Abstract: A semiconductor device that generates a clock which is synchronized with a reference signal stably and with fixed synchronization accuracy, and enables to deal with an abrupt variation in the reference signal. This semiconductor device includes N stages of delay elements each delaying an external clock by 1/N clock (N: an integer that is two or larger); a phase comparator for comparing the phase of a clock that has been delayed by the N stages of the delay elements with the phase of the external clock one clock late; a controller that receives a phase difference detected by the phase comparator and controls respective delays of the delay elements; and a selector for selecting a delayed clock having the closest phase to the reference signal from delayed clocks which are generated by the N stages of the delay elements, respectively, and shifted in phase with each other by 1/N clock.

Abstract: A pre-charge circuit capable of pre-charging a high-impedance node of an operation circuit to a target voltage when a pre-charge signal driving the pre-charge circuit is enabled.

Abstract: In a class of embodiments, an adaptive equalization circuit that implements a joint adaptation algorithm. Other embodiments are receivers that include such an adaptive equalization circuit, and joint adaptation equalization methods. The equalization circuit includes a filter having a low-frequency-gain path (sometimes referred to as a low-frequency filter) and a high-frequency-boosting path (sometimes referred to as a high-frequency filter). The high-frequency filter typically includes a high-pass filter in series with an amplifier having adjustable gain. A high-frequency-boosting tuning loop controls the adjustable gain applied by the high-frequency filter. A low-frequency-gain tuning loop controls the adjustable gain applied by the low-frequency filter.

Abstract: In a &pgr;/2 phase shifter, first and second signals and first and second inverted signals are produced based on input signals. The first and second signals have the same amplitude and are out of phase from each other, and the first and second inverted signals respectively correspond to the first and second signals with their respective phases inverted. A first output signal is produced by adding the first signal and the second signal, and a second output signal is produced by adding the first signal and the second inverted signal. Since the first and second signals have the same amplitude, the first output signal and the second output signal respectively correspond to diagonal lines of a rhombus formed by a vector representing the first signal and a vector representing the second signal. Accordingly, the phase difference between the first and second output signals of the &pgr;/2 phase shifter is accurately set to &pgr;/2 even when the phase difference between the first and second signals is not &pgr;/2.

Abstract: The amplifier of the present invention causes variations in the rail voltage that are controlled by the frequency of the audio signal being amplified as the audio signal changes. This is done to tune the operation of the amplifier taking into consideration the frequency response of the human ear. By doing so, the resulting amplifier is more efficient at lower frequencies where more signal distortion is required before it can be heard by the human ear, and a higher quality signal output is provided at higher frequencies where the human ear can more readily detect distortion. Thus by designing the amplifier from the listener's point of view results in an amplifier with much improved performance from both technical and listener points of view.

Abstract: Methods and systems for controlling delay relatively independent of process, supply-voltage, and/or temperature (“PVT”) variations include sensing an output signal after a number of inverters and activating different numbers of transistors and/or adjusting strength of transistors in a delay path to compensate for PVT variations. In an embodiment, a waveform is received, delayed, and output to an output terminal using at least one relatively low-power device. Supplemental output power is provided by at least one relatively high-power device until the output waveform exceeds a threshold.

Abstract: A phase locked loop (PLL), which has high operation speed and high resolution, and is particularly applicable in high frequency process, is disclosed. The PLL, receiving a data signal and generating a clock signal, comprises a voltage controlled oscillator (VCO) and multi-phase generator (MPG), a transition detector, an optimal phase encoder, and a phase selector, wherein the four devices are respectively used for outputting N phase clock signals of same frequency but different phases, for outputting a data period value and a clock period value by receiving the N phase clock signals, the data signal and the clock signal, for outputting a phase select signal according to the data period value and the clock period value, and for outputting one of the phase clock signals according to the phase select signal.