Patents Examined by Linh M. Nguyen
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Patent number: 6816007Abstract: The amplifier of the present invention causes variations in the rail voltage that are controlled by the frequency of the audio signal being amplified as the audio signal changes. This is done to tune the operation of the amplifier taking into consideration the frequency response of the human ear. By doing so, the resulting amplifier is more efficient at lower frequencies where more signal distortion is required before it can be heard by the human ear, and a higher quality signal output is provided at higher frequencies where the human ear can more readily detect distortion. Thus by designing the amplifier from the listener's point of view results in an amplifier with much improved performance from both technical and listener points of view.Type: GrantFiled: July 29, 2002Date of Patent: November 9, 2004Inventor: Joseph Y. Sahyoun
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Patent number: 6815987Abstract: A phase locked loop (PLL), which has high operation speed and high resolution, and is particularly applicable in high frequency process, is disclosed. The PLL, receiving a data signal and generating a clock signal, comprises a voltage controlled oscillator (VCO) and multi-phase generator (MPG), a transition detector, an optimal phase encoder, and a phase selector, wherein the four devices are respectively used for outputting N phase clock signals of same frequency but different phases, for outputting a data period value and a clock period value by receiving the N phase clock signals, the data signal and the clock signal, for outputting a phase select signal according to the data period value and the clock period value, and for outputting one of the phase clock signals according to the phase select signal.Type: GrantFiled: October 24, 2002Date of Patent: November 9, 2004Assignee: Mediatek Inc.Inventors: Tse-Hsiang Hsu, Chih-Cheng Chen
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Patent number: 6815995Abstract: Methods and systems for controlling delay relatively independent of process, supply-voltage, and/or temperature (“PVT”) variations include sensing an output signal after a number of inverters and activating different numbers of transistors and/or adjusting strength of transistors in a delay path to compensate for PVT variations. In an embodiment, a waveform is received, delayed, and output to an output terminal using at least one relatively low-power device. Supplemental output power is provided by at least one relatively high-power device until the output waveform exceeds a threshold.Type: GrantFiled: September 15, 2003Date of Patent: November 9, 2004Assignee: Broadcom CorporationInventor: Janardhanan S. Ajit
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Patent number: 6812789Abstract: A method and apparatus for maintaining approximately constant gain of an RF power amplifier includes a digital control module for modifying gain parameters of the power amplifier to provide a constant fixed power gain over the entire frequency range of operation. The digital control module compares stored frequency response parameters, which are indicative of the inherent closed-loop gain of the power amplifier, with the current selected gain and carrier frequency setting to generate a digital gain control value. The digital gain control value is used to modify a detected input RF envelope in the power amplifier analog loop. The modified input envelope is compared with an envelope of the transmitted RF signal to adjust the gain of the power amplifier. Optionally, the detected RF input envelope may be sampled to digitally compensate for variations in the RF input signal.Type: GrantFiled: July 18, 2002Date of Patent: November 2, 2004Assignee: Harris CorporationInventors: Christopher David Mackey, Brian Christopher Boorman, Thomas Daniel O Brien
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Patent number: 6812750Abstract: A clock signal is generated in a remote circuit location by generating a source clock signal, providing at least one digital control signal for determining a ratio between a frequency of the clock signal and the source clock signal, transmitting the source clock signal and the at least one digital control signal to the remote circuit region in which the clock signal is to be used, and generating the clock signal in the remote circuit location based on the source clock signal and the at least one digital control signal.Type: GrantFiled: June 13, 2003Date of Patent: November 2, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Carson Donahue Henrion, Gary Lewis Taylor
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Patent number: 6809566Abstract: A differential-to-single-ended (DSE) converter receives a positive differential input and a negative differential input and generates a single-ended output. The DSE converter comprises: 1) a first comparator having a non-inverting input coupled to the positive differential input and an inverting input coupled to the negative differential input; 2) a second comparator having an inverting input coupled to the positive differential input and a non-inverting input coupled to the negative differential input; 3) a first D flip-flop having a Logic 1 input and clocked by a rising edge on the first comparator output; 4) a second D flip-flop having a Logic 1 input and clocked by a rising edge on the second comparator output; and 5) a latch circuit having a first input coupled to the first D flip-flop output and a second input coupled to the second D flip-flop output. Rising edges on the first and second D flip-flop outputs cause the latch output to change state.Type: GrantFiled: July 30, 2003Date of Patent: October 26, 2004Assignee: National Semiconductor CorporationInventor: Jane Xin-LeBlanc
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Patent number: 6809564Abstract: The present invention includes an integrated circuit that can use a high-frequency timing reference generator from a high-speed serial interface to provide the clocking and timing requirements for the integrated circuit. The timing mechanism in the present invention obviates the need for phase locked loop (PLL) macrocells to provide timing reference and timing signals in the IC. The ICs of the present invention are preferably used as disk drive integrated circuits that include DSP, memory, data path controllers, data interfaces, custom macrocells, and DSP peripherals. The high-speed serial interface is preferably a Serial ATA (SATA), Universal Serial Bus (USB), Fiber Channel, or Serial Attached SCSI (SAS), among others.Type: GrantFiled: July 17, 2002Date of Patent: October 26, 2004Assignee: STMicroelectronics, Inc.Inventor: John P. Hill
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Patent number: 6809555Abstract: Simple, glitch-free phase detector circuits provide add and subtract output signals indicating the phase relationship between two input clock signals. Some embodiments also provide a lock output signal having a lock window, and in some of these embodiments, the size of the lock window is programmable. An optionally delayed version of the feedback clock signal is stored a first time when the input clock signal goes high, then stored a second time after a predetermined delay. In some embodiments, the predetermined delay is programmable. When both stored values are low, the subtract output signal is active. When the first stored value is high, the add output signal is active, regardless of the state of the second stored value. When the first stored value is low and the second stored value is high, the two clocks are synchronized and the phase detector indicates a lock condition.Type: GrantFiled: May 2, 2003Date of Patent: October 26, 2004Assignee: Xilinx, Inc.Inventor: Andy T. Nguyen
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Patent number: 6806786Abstract: Techniques to select the proper frequency band for use in a PLL from among multiple frequency bands of a multi-band VCO. The PLL comprises a detector, a loop filter, the multi-band VCO, and a control unit. The detector receives a first signal to be locked to and a second signal that is related to a VCO signal and provides a detector output. The loop filter filters the detector output to provide a control signal. The multi-band VCO selects one of the multiple frequency bands based on a select signal and provides the VCO signal at a frequency determined by the control signal. The control unit derives the select signal for the multi-band VCO based on information extracted from a third signal (e.g., a filtered version of the control signal) and a timing signal from a timer unit.Type: GrantFiled: May 9, 2002Date of Patent: October 19, 2004Assignee: RF Micro Devices, Inc.Inventors: Christopher Lam, Thai Nguyen, Chet Sooraparth
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Patent number: 6806748Abstract: A sinusoidal signal multiplier circuit produces an output sinusoidal signal substantially without any DC component. This sinusoidal signal multiplier circuit includes a first multiplication cell receiving a first sinusoidal signal at a first input and a second sinusoidal signal at a second input. The first multiplication cell delivers a first output signal. The sinusoidal signal multiplier circuit also includes a second multiplication cell, identical to the first multiplication cell, that receives the second sinusoidal signal at its first input and the first sinusoidal signal at its second input, and delivers a second output signal. The sinusoidal signal multiplier circuit also includes an adder circuit to add the first output signal and the second output signal to provide from the sinusoidal signal multiplier circuit an output signal substantially without any DC component.Type: GrantFiled: March 19, 2002Date of Patent: October 19, 2004Assignee: STMicroelectronics S.A.Inventor: Luc Garcia
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Patent number: 6806746Abstract: A direct frequency synthesizer provides an output signal derived from a high frequency reference signal that is frequency divided and mixed to satisfy the coarse step synthesis requirements of an offset loop synthesizer. The absence of a VCO within the direct frequency synthesizer, provides the direct frequency synthesizer with lower phase noise than a typical PLL-based coarse step synthesizer. Though applicable to a variety of types of synthesizers and signal generators, the direct frequency synthesizer provides especially advantageous noise performance when used to generate an offset signal for an offset loop synthesizer of the first local oscillator of a spectrum analyzer, where the second local oscillator of the spectrum analyzer provides the reference signal for the direct frequency synthesizer.Type: GrantFiled: July 31, 2003Date of Patent: October 19, 2004Assignee: Agilent Technologies, Inc.Inventor: Wing J. Mar
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Patent number: 6806753Abstract: A delay circuit, including a plurality of delay blocks connected in series, each having a first complementary input terminal to which a first complementary signal is inputted, a second complementary input terminal to which a second complementary signal is inputted, and a complementary output terminal which outputs a third complementary signal delaying by selecting one of the first and second complementary signals based on logic of a delay selection signal, the complementary output terminal of the delay blocks except for the delay block of last stage being connected to the second complementary input terminal of the subsequent delay block, respectively, a complementary delay signal delaying the first complementary signal in accordance with logic of the delay selection signal being outputted from the complementary output terminal of the delay block of last stage, and the same first complementary signal is inputted to the first complementary input terminals of the plurality of delay blocks, respectively.Type: GrantFiled: October 25, 2002Date of Patent: October 19, 2004Assignee: Kabushiki Kaisha ToshibaInventor: Atsushi Kawasumi
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Patent number: 6804812Abstract: A programmable logic array (PLA) in accordance with the invention achieves a maximum amount of depopulation of programmable connections while still implementing a logic function and maintaining flexibility for future reprogramming. In addition, a PLA in accordance with the invention can be built so that no matter what functionality is programmed, performance characteristics for the device are maintained. Further, a PLA in accordance with the invention does not require a regular array structure.Type: GrantFiled: June 10, 2003Date of Patent: October 12, 2004Assignee: Lightspeed Semiconductor CorporationInventors: Robert Osann, Jr., Patrick Hallinan, Jung Lee, Shridhar Mukund
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Patent number: 6801068Abstract: The invention discloses a delay clock pulse-width adjusting circuit. The circuit comprises: a power supply; a delay comparator, which one input terminal inputs a sine wave signal and another input terminal inputs a compare voltage, which output terminal outputs a clock signal with a defined duty-ratio; and a converting circuit, converting the clock signal to a DC level, which input terminal is connected to the output terminal of the delay comparator, which output terminal is connected to the another input terminal of the delay comparator. With the circuit, the duty-ratio of a clock signal is no longer abrupt change, so burden of the digital signal processing is decreased. Consequently, the adjusting circuit satisfies requirements: high traffic, low error rate and high stability of the clock signal duty-ratio.Type: GrantFiled: October 24, 2002Date of Patent: October 5, 2004Assignee: Huawei Technologies Co., Ltd.Inventor: Dengqing Yin
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Patent number: 6801067Abstract: A method of generating a clock may use an analog synchronous mirror delay (ASMD) circuit with a duty cycle correction scheme, and an internal clock generator may use one or more of the ASMD circuits, The ASMD circuit may include a comparator with first and second input terminals that generates an output clock based on a comparison result between a signal on the first input terminal and a signal on the second input terminal, a first precharge circuit connected to the first input terminal and precharging the first input terminal, and a second precharge circuit connected to the second input terminal and precharging the second input terminal. The ASMD circuit may also include a first pair of discharge circuits discharging the first input terminal within first and second cycles of the input clock, and a second pair of discharge circuits discharging the second input terminal within first and second cycles of the input clock.Type: GrantFiled: April 2, 2003Date of Patent: October 5, 2004Assignee: Samsung Electronics Co., Ltd.Inventor: Seong-Jin Jang
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Patent number: 6801105Abstract: The invention relates to a dielectric double-mode resonator of a radio-frequency filter that comprises a block structure comprising at least two resonator structures having at least one resonance mode each. In addition, said block structure comprises a cavity wall that limits a cavity at least partly inside the block structure, the cavity affecting the resonance modes of the at least two resonator structures. The block structure comprises a first block and a second block set against each other and each comprising at least part of the at least two resonator structures and at least part of the cavity wall limiting the cavity.Type: GrantFiled: April 1, 2003Date of Patent: October 5, 2004Assignee: Remec OyInventor: Kimmo Karhu
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Patent number: 6801073Abstract: The present invention is a system, circuit and method for low voltage operable, small footprint delay. The delay circuit of the present invention uses an input switching configuration with a limited gate to source conductance to enhance the delay time for any given resistor and capacitor area in an RC network. According to the delay circuit of the present invention, the output of the RC network transitions very slowly in order to achieve a long delay. When the next stage of the delay circuit trips, the limited gate to source conductance is bypassed to allow rapid full rail presetting or resetting on the output of the RC network. This rapid full rail presetting or resetting limits power consumption and rapidly prepares the delay circuit for the next edge transition or cycle. Methods and systems incorporating the delay circuit and techniques of the present invention are also disclosed.Type: GrantFiled: June 25, 2002Date of Patent: October 5, 2004Assignee: Micron Technology, Inc.Inventor: Donald M. Morgan
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Patent number: 6798261Abstract: A method for characterizing a change in delay induced by a switching history of a circuit includes the steps of generating a first signal having a pulse width that is selectively adjustable, the first signal having a first edge and a second edge associated therewith, the first and second edges being opposite in polarity with respect to one another; generating a second signal having a first switch delay characteristic of the first edge of the first signal and a second switch delay characteristic of the second edge of the first signal, wherein the pulse width of the first signal is less than the first switch delay associated with the second signal; varying the pulse width of the first signal; monitoring the second signal; determining a value of the pulse width that defines a boundary of when the second signal is present and when the second signal is not present; and determining a ratio of the value of the pulse width that defines the boundary to the first switch delay and/or the second switch delay, whereby theType: GrantFiled: May 22, 2003Date of Patent: September 28, 2004Assignee: International Business Machines CorporationInventors: Manjul Bhushan, Mark B. Ketchen, Dale J. Pearson
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Patent number: 6798268Abstract: The present invention relates to circuits having differential structure which uses complementary devices for processing single-ended signal. The single-ended differential circuit in accordance with the present invention, comprises first and second complementary devices having first, second, and third terminals, respectively, wherein current flowing from the second terminal to the third terminal has its quantity and direction being varying in dependant on the voltage driven to the first terminal, wherein the currents flowing through the first and second complementary devices vary in opposite relationship.Type: GrantFiled: November 18, 2003Date of Patent: September 28, 2004Assignee: Integrant Technologies Inc.Inventors: Bonkee Kim, Iiku Nam, Kwyro Lee
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Patent number: 6794917Abstract: The on-time of a pulse signal is controlled by comparing a ramp signal to an input signal that is dynamically selected from two signals. A first operating mode is active when a clock signal is in a first logic state, where the pulse signal is reset. A second operating mode is initiated when the clock signal changes from the first logic state to a second logic state. During the second operating mode, the ramp signal is compared to the first signal. A third operating mode is initiated when the ramp signal exceeds the first signal during the second operating mode. During the third operating mode, the pulse signal is set and the ramp signal is compared to the second signal. The pulse signal is reset when the when the ramp signal exceeds the second signal in the third operating mode such that the on-time of the pulse signal is controlled.Type: GrantFiled: July 14, 2003Date of Patent: September 21, 2004Assignee: National Semiconductor CorporationInventors: Steven Michael Barrow, Robert Kenneth Oppen, Steven Harris