Abstract: A transimpedance amplifier (18) receives an audio signal from a power audio amplifier (14) and provides a variable power level to a loudspeaker (16). A first variable gain amplifier (28) receives the audio signal and provides a variable gain to a power amplifier (40). The output signal of the power amplifier drives the loudspeaker. A sense amplifier (52) subtracts a voltage representative of current flowing through the loudspeaker from a voltage applied to the loudspeaker and provides a difference signal. A second variable gain amplifier (70) receives the difference signal and provides a variable gain to a load amplifier (80). The gains of the first and second variable gain amplifiers are inversely proportional. A resistive element (84) having a real impedance is coupled between an output of the load amplifier and the input of the transimpedance amplifier to maintain the complex impedance of the loudspeaker at the output of the power audio amplifier.

Abstract: A method and apparatus for maintaining approximately constant gain of an RF power amplifier includes a digital control module for modifying gain parameters of the power amplifier to provide a constant fixed power gain over the entire frequency range of operation. The digital control module compares stored frequency response parameters, which are indicative of the inherent closed-loop gain of the power amplifier, with the current selected gain and carrier frequency setting to generate a digital gain control value. The digital gain control value is used to modify a detected input RF envelope in the power amplifier analog loop. The modified input envelope is compared with an envelope of the transmitted RF signal to adjust the gain of the power amplifier. Optionally, the detected RF input envelope may be sampled to digitally compensate for variations in the RF input signal.

Abstract: A clock signal is generated in a remote circuit location by generating a source clock signal, providing at least one digital control signal for determining a ratio between a frequency of the clock signal and the source clock signal, transmitting the source clock signal and the at least one digital control signal to the remote circuit region in which the clock signal is to be used, and generating the clock signal in the remote circuit location based on the source clock signal and the at least one digital control signal.

Abstract: A differential-to-single-ended (DSE) converter receives a positive differential input and a negative differential input and generates a single-ended output. The DSE converter comprises: 1) a first comparator having a non-inverting input coupled to the positive differential input and an inverting input coupled to the negative differential input; 2) a second comparator having an inverting input coupled to the positive differential input and a non-inverting input coupled to the negative differential input; 3) a first D flip-flop having a Logic 1 input and clocked by a rising edge on the first comparator output; 4) a second D flip-flop having a Logic 1 input and clocked by a rising edge on the second comparator output; and 5) a latch circuit having a first input coupled to the first D flip-flop output and a second input coupled to the second D flip-flop output. Rising edges on the first and second D flip-flop outputs cause the latch output to change state.

Abstract: Simple, glitch-free phase detector circuits provide add and subtract output signals indicating the phase relationship between two input clock signals. Some embodiments also provide a lock output signal having a lock window, and in some of these embodiments, the size of the lock window is programmable. An optionally delayed version of the feedback clock signal is stored a first time when the input clock signal goes high, then stored a second time after a predetermined delay. In some embodiments, the predetermined delay is programmable. When both stored values are low, the subtract output signal is active. When the first stored value is high, the add output signal is active, regardless of the state of the second stored value. When the first stored value is low and the second stored value is high, the two clocks are synchronized and the phase detector indicates a lock condition.

Abstract: The present invention includes an integrated circuit that can use a high-frequency timing reference generator from a high-speed serial interface to provide the clocking and timing requirements for the integrated circuit. The timing mechanism in the present invention obviates the need for phase locked loop (PLL) macrocells to provide timing reference and timing signals in the IC. The ICs of the present invention are preferably used as disk drive integrated circuits that include DSP, memory, data path controllers, data interfaces, custom macrocells, and DSP peripherals. The high-speed serial interface is preferably a Serial ATA (SATA), Universal Serial Bus (USB), Fiber Channel, or Serial Attached SCSI (SAS), among others.

Abstract: Techniques to select the proper frequency band for use in a PLL from among multiple frequency bands of a multi-band VCO. The PLL comprises a detector, a loop filter, the multi-band VCO, and a control unit. The detector receives a first signal to be locked to and a second signal that is related to a VCO signal and provides a detector output. The loop filter filters the detector output to provide a control signal. The multi-band VCO selects one of the multiple frequency bands based on a select signal and provides the VCO signal at a frequency determined by the control signal. The control unit derives the select signal for the multi-band VCO based on information extracted from a third signal (e.g., a filtered version of the control signal) and a timing signal from a timer unit.

Abstract: A delay circuit, including a plurality of delay blocks connected in series, each having a first complementary input terminal to which a first complementary signal is inputted, a second complementary input terminal to which a second complementary signal is inputted, and a complementary output terminal which outputs a third complementary signal delaying by selecting one of the first and second complementary signals based on logic of a delay selection signal, the complementary output terminal of the delay blocks except for the delay block of last stage being connected to the second complementary input terminal of the subsequent delay block, respectively, a complementary delay signal delaying the first complementary signal in accordance with logic of the delay selection signal being outputted from the complementary output terminal of the delay block of last stage, and the same first complementary signal is inputted to the first complementary input terminals of the plurality of delay blocks, respectively.

Abstract: A direct frequency synthesizer provides an output signal derived from a high frequency reference signal that is frequency divided and mixed to satisfy the coarse step synthesis requirements of an offset loop synthesizer. The absence of a VCO within the direct frequency synthesizer, provides the direct frequency synthesizer with lower phase noise than a typical PLL-based coarse step synthesizer. Though applicable to a variety of types of synthesizers and signal generators, the direct frequency synthesizer provides especially advantageous noise performance when used to generate an offset signal for an offset loop synthesizer of the first local oscillator of a spectrum analyzer, where the second local oscillator of the spectrum analyzer provides the reference signal for the direct frequency synthesizer.

Abstract: A sinusoidal signal multiplier circuit produces an output sinusoidal signal substantially without any DC component. This sinusoidal signal multiplier circuit includes a first multiplication cell receiving a first sinusoidal signal at a first input and a second sinusoidal signal at a second input. The first multiplication cell delivers a first output signal. The sinusoidal signal multiplier circuit also includes a second multiplication cell, identical to the first multiplication cell, that receives the second sinusoidal signal at its first input and the first sinusoidal signal at its second input, and delivers a second output signal. The sinusoidal signal multiplier circuit also includes an adder circuit to add the first output signal and the second output signal to provide from the sinusoidal signal multiplier circuit an output signal substantially without any DC component.

Abstract: A programmable logic array (PLA) in accordance with the invention achieves a maximum amount of depopulation of programmable connections while still implementing a logic function and maintaining flexibility for future reprogramming. In addition, a PLA in accordance with the invention can be built so that no matter what functionality is programmed, performance characteristics for the device are maintained. Further, a PLA in accordance with the invention does not require a regular array structure.

Abstract: The invention discloses a delay clock pulse-width adjusting circuit. The circuit comprises: a power supply; a delay comparator, which one input terminal inputs a sine wave signal and another input terminal inputs a compare voltage, which output terminal outputs a clock signal with a defined duty-ratio; and a converting circuit, converting the clock signal to a DC level, which input terminal is connected to the output terminal of the delay comparator, which output terminal is connected to the another input terminal of the delay comparator. With the circuit, the duty-ratio of a clock signal is no longer abrupt change, so burden of the digital signal processing is decreased. Consequently, the adjusting circuit satisfies requirements: high traffic, low error rate and high stability of the clock signal duty-ratio.

Abstract: The invention relates to a dielectric double-mode resonator of a radio-frequency filter that comprises a block structure comprising at least two resonator structures having at least one resonance mode each. In addition, said block structure comprises a cavity wall that limits a cavity at least partly inside the block structure, the cavity affecting the resonance modes of the at least two resonator structures. The block structure comprises a first block and a second block set against each other and each comprising at least part of the at least two resonator structures and at least part of the cavity wall limiting the cavity.

Abstract: The present invention is a system, circuit and method for low voltage operable, small footprint delay. The delay circuit of the present invention uses an input switching configuration with a limited gate to source conductance to enhance the delay time for any given resistor and capacitor area in an RC network. According to the delay circuit of the present invention, the output of the RC network transitions very slowly in order to achieve a long delay. When the next stage of the delay circuit trips, the limited gate to source conductance is bypassed to allow rapid full rail presetting or resetting on the output of the RC network. This rapid full rail presetting or resetting limits power consumption and rapidly prepares the delay circuit for the next edge transition or cycle. Methods and systems incorporating the delay circuit and techniques of the present invention are also disclosed.

Abstract: A method of generating a clock may use an analog synchronous mirror delay (ASMD) circuit with a duty cycle correction scheme, and an internal clock generator may use one or more of the ASMD circuits, The ASMD circuit may include a comparator with first and second input terminals that generates an output clock based on a comparison result between a signal on the first input terminal and a signal on the second input terminal, a first precharge circuit connected to the first input terminal and precharging the first input terminal, and a second precharge circuit connected to the second input terminal and precharging the second input terminal. The ASMD circuit may also include a first pair of discharge circuits discharging the first input terminal within first and second cycles of the input clock, and a second pair of discharge circuits discharging the second input terminal within first and second cycles of the input clock.

Abstract: A method for characterizing a change in delay induced by a switching history of a circuit includes the steps of generating a first signal having a pulse width that is selectively adjustable, the first signal having a first edge and a second edge associated therewith, the first and second edges being opposite in polarity with respect to one another; generating a second signal having a first switch delay characteristic of the first edge of the first signal and a second switch delay characteristic of the second edge of the first signal, wherein the pulse width of the first signal is less than the first switch delay associated with the second signal; varying the pulse width of the first signal; monitoring the second signal; determining a value of the pulse width that defines a boundary of when the second signal is present and when the second signal is not present; and determining a ratio of the value of the pulse width that defines the boundary to the first switch delay and/or the second switch delay, whereby the

Abstract: The present invention relates to circuits having differential structure which uses complementary devices for processing single-ended signal. The single-ended differential circuit in accordance with the present invention, comprises first and second complementary devices having first, second, and third terminals, respectively, wherein current flowing from the second terminal to the third terminal has its quantity and direction being varying in dependant on the voltage driven to the first terminal, wherein the currents flowing through the first and second complementary devices vary in opposite relationship.

Abstract: The on-time of a pulse signal is controlled by comparing a ramp signal to an input signal that is dynamically selected from two signals. A first operating mode is active when a clock signal is in a first logic state, where the pulse signal is reset. A second operating mode is initiated when the clock signal changes from the first logic state to a second logic state. During the second operating mode, the ramp signal is compared to the first signal. A third operating mode is initiated when the ramp signal exceeds the first signal during the second operating mode. During the third operating mode, the pulse signal is set and the ramp signal is compared to the second signal. The pulse signal is reset when the when the ramp signal exceeds the second signal in the third operating mode such that the on-time of the pulse signal is controlled.

Abstract: A charge-pump circuit for charge-share suppression. A first switching element is coupled between a first connecting node and an output terminal. A first load receives a current from a first current source and outputs an output voltage at the output terminal when the first switching element is in “On” state. A status of a second switching element is controlled by the input signal and opposite to the status of the first switching elements A second current source is coupled to the second switching element through a second connecting node. A second load receives the output voltage when the second switching element is in “On” state. A first feedback circuit maintains a constant relation between the output voltage and a voltage of the first node. A second feedback circuit maintains a constant relation between the output voltage and a voltage of the second node.

Abstract: An oscillation circuit is provided with a positive feedback oscillation loop constructed by an amplifier, a SAW resonator with a prescribed resonance frequency, a phase-shifting circuit which outputs the phase of an input signal as an output signal with a prescribed shift and a tank circuit composed of an inductance element and a capacitive element, and an NTC thermistor with negative temperature characteristics is connected in parallel to the tank circuit. Moreover, a capacitive element with a capacity-temperature characteristic for correcting the quadratic frequency-temperature characteristic of the SAW resonator is used in the oscillation circuit as the oscillation element of the tank circuit.