Abstract: An integrated circuit includes clock deskew circuitry. The deskew circuitry includes multiple loop circuits to align a received clock with a data eye, and to reduce the effects of clock drift caused by voltage and temperature variations. The loop circuits include phase interpolators to produce local clock signals. Local clock signals are provided to seqiuential elements through local clock trees and are also provided to a phase detector through a dummy local clock tree. The operation of the phase interpolators is influenced by the phase detector.

Abstract: In a digital pulse width modulation generator unit, a phase register is coupled to the clocked counter providing the generator unit time base. In response to a control signal, the contents of the phase register over-write the present counter, thereby changing the phase of pulse width modulated generator output signal. When a plurality of pulse width modulated generator units, the phases of the units can be controlled relative to a reference generator. The contents of the phase register can be altered by hardware or by software.

Abstract: A pulse on edge circuit includes a first pull up transistor having its gate terminal coupled to a delayed control signal and a second pull up transistor having its gate terminal coupled to an inverted delayed control signal. A first and second pull down transistors are coupled in series between the first pull up transistor and a low voltage bias, wherein the gates of the first and second pull down transistors are coupled to the delayed control signal and inverted control signal, respectively. A third and fourth pull down transistors are coupled in series between the second pull up transistor and the low voltage bias. The gates of the third and fourth pull down transistors are coupled to a control signal and the inverted delayed control signal, respectively.

Abstract: The present invention relates to a duty cycle correction circuit of a DLL circuit. According to the present invention, in an Active Power-Down Mode (APDM), a voltage comparator of a duty cycle correction circuit operates without being reset. Therefore, although an internal power supply voltage is instantly changed in the APDM, the duty cycle of a DLL clock can be accurately set to 50%.

Abstract: An apparatus comprising a phase lock loop circuit and a control circuit. The phase lock loop circuit configured to generate an output signal having a first frequency in response to (i) an input signal having a second frequency, (ii) a first divider value and (iii) a second divider value. The second divider value may control spread spectrum modulation of the phase lock loop circuit. The control circuit configured to generate the second divider value in response to (i) the output signal and (ii) a programmable control signal.

Abstract: A fast lock mechanism for delay lock loops and phase lock loops. A first circuit is coupled to receive an input clock signal and to generate an output clock signal responsive to the input clock signal. The first circuit includes a charge pump and delay cells. The charge pump generates an operational bias voltage during operation of the first circuit to control a delay of the delay cells. A fast lock circuit is coupled to an output of the charge pump to precharge the output of the charge pump with a startup bias voltage prior to enabling the charge pump.

Abstract: A low-power consumption level shifter circuit is provided by preventing a through current which is generated when a level of a signal is changed. In order to prevent a through current which flows when a level of a signal of the input is changed, the p-channel TFTs are controlled so that the p-channel TFTs and the n-channel TFT or the p-channel TFTs and the n-channel TFT are not turned on at once. A high level signal is inputted to the gate of the n-channel TFT, and at the moment when the n-channel TFT is turned on, the p-channel TFT is turned off. Similarly, at the moment when the n-channel TFT is turned on, the p-channel TFT is turned off. The p-channel TFTs and the n-channel TFT, or the p-channel TFTs and the n-channel TFT are not turned on at once, thereby a path in which the through current flows is cut off.

Abstract: A DLL includes a control module coupled with a phase detect signal. The phase detect signal is used by a control module to generate feedback and output select signals. The feedback and output select signals are each coupled to a multiplexer. Each multiplexer is coupled to a Multi-Tap Delay Line (MTDL). The MTDL provides a plurality of delayed signals that are selectable by the two multiplexers. The first multiplexer, coupled to the feedback select signal, selects a feedback clock signal. The second multiplexer, coupled to the output select signal, select a DLL output signal. The control module may receive other signals, such as a delay select signal, that may be used to program or set the delay of the output signal. In addition, a plurality of output signals may be available from the DLL.

Abstract: A delay locked loop circuit with a first flip flop driven by a 0° clock and receiving the input data. A second flip flop by a 180° clock and receiving the input data. A first demultiplexer receives an output of the first flip flop and outputs peak data. A second demultiplexer receives an output of the second flip flop and outputs zero data. A timing recovery circuit outputs phase control bits based on the zero data and the peak data. A first phase interpolator outputs the 0° clock based on the phase control signal. A second phase interpolator outputs the 180° clock based on the phase control signal. A phase register receives the phase control signal from the timing recovery circuit. The first and second flip flops can be D flip flops. The first and second phase interpolators adjust relative phases of the 0° clock and 180° clock based on the phase control signal.

Abstract: An integrated circuit device is provided which can increase a stable area having less digital noise. A data delay adjustment circuit group (110) is fed with data outputted from a flip-flop circuit group (106), adjusts a delay of the data so as to synchronize the operation of a data output terminal group (114) with the operation of a logic circuit (100), and outputs the data to the data output terminal group (114). A clock delay adjustment circuit (109) similarly adjusts a delay of a clock outputted from an inverter (105) and outputs the clock to a clock output terminal (113). Therefore, the operations of data output terminals are synchronized with the operation of the logic circuit (100) while keeping the phase relationship between an external output clock and external output data.

Abstract: A clock switching device capable of automatic switching to a clock distribution system for back-up without interrupting processing of the device, which includes an abnormality detection unit which detects lack of coincidence in a logical level between a current clock pulse and a one-cycle preceding clock pulse as abnormality in a waveform on the basis of a plurality of cock pulses, a phase adjustment unit for switching which adjusts a phase of other clock pulse to a phase of a clock pulse being output, and a switching unit which switches to and outputs other clock pulse whose phase is adjusted by the phase adjustment unit for switching based on detection of lack of coincidence in a logical level by said abnormality detection unit.

Abstract: A signal processing apparatus includes: (a) A signal treating unit for effecting signal treating functions to present a treated signal at an output. (b) A clock generator receiving a clock signal and using the clock signal for presenting an internal clock signal for use by the signal treating unit. (c) A clock simulating unit occasionally coupled with at least one of the clock signal and the clock generator provides a simulated clock signal generally similar to the internal clock signal when either of the clock signal or the internal clock signal is interrupted. (d) A control unit coupled with the signal treating unit, at least one of the clock signal input locus and the internal clock generator for selectively coupling one of the internal clock signal and the simulated clock signal for use by the signal treating unit.

Abstract: Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles. The state machine generates a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal, the clock high signal and the clock low signal having patterns derived from a waveform of a target divided ratio clock, the clock high signal and the clock low signals have patterns that match the targeted divided clock frequency and duty cycle. A local pass gate receives the clock low signal and the clock high signal and generates an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

Abstract: In one embodiment of the invention, a pulse-generation circuit for generating control signals has clock-delay circuitry for generating a plurality of differently delayed clock signals. Each control signal is generated by a set-reset latch that receives its set and reset signals from different pulse generators operating based on different delayed clock signals from the clock-delay circuitry. In one implementation, the clock-delay circuitry has a partitioned delay block in which different sub-blocks provide different delay functionality to provide the clock-delay circuitry with programmable flexibility.

Abstract: A duty cycle corrector includes a first controllable delay, a second controllable delay, a phase detector, and a compensation circuit. The first controllable delay is configured to delay a first signal to provide a second signal. The second controllable delay is configured to delay the second signal to provide a third signal. The phase detector is configured to adjust the first controllable delay and the second controllable delay to phase lock the third signal to the first signal. The compensation circuit is configured to compensate for a mismatch between the first controllable delay and the second controllable delay to provide a fourth signal in response to the first signal and a fifth signal approximately 180 degrees out of phase with the fourth signal in response to the second signal.

Abstract: A voltage divider device includes a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region. An input voltage is coupled between the first and second gates, and an output voltage is taken from at least one of a source of the FET and a drain of the FET, wherein the output voltage represents a divided voltage with respect to the input voltage.

Abstract: A system and method for providing a voltage. The system includes a first transistor with a first gate, a first terminal, and a second terminal, a second transistor with a second gate, a third terminal, and a fourth terminal, and a third transistor with a third gate, a fifth terminal, and a sixth terminal. Additionally, the system includes a fourth transistor with a fourth gate, a seventh terminal, and an eighth terminal, a fifth transistor with a fifth gate, a ninth terminal, and a tenth terminal, and a sixth transistor with a sixth gate, an eleventh terminal, and a twelfth terminal. The tenth terminal and the eleventh terminal are directly connected at a third node, which is directly connected to a first substrate for the third transistor, a second substrate for the fourth transistor, a third substrate for the fifth transistor, and a fourth substrate for the sixth transistor.

Abstract: A phase-locked loop (“PLL”) for use in a programmable logic device (“PLD”) is constructed with modular components, which may be digital, and which may be programmable or adjustable, in place of the conventional analog charge pump and loop filter. Connections are provided between those components and the remainder of the PLD so that if the PLL is not being used in a particular user design of the PLD, the PLL modular components may be used by other portions of the PLD. Similarly, those connections allow other portions of the PLD to be used in place of one or more of the modular components where more complex or special filtering than can be provided by the modular components is required.

Abstract: p-channel MOS transistors are turned on alternatively when a positive phase signal and an opposite phase signal each generated from a first voltage signal. Moreover, n-channel MOS transistors are turned on alternatively when a positive phase signal and an opposite phase signal each generated from a second voltage signal. When being turned on, the p-channel MOS transistors supply current to transmission lines, respectively. When being turned on, the n-channel MOS transistors discharge current supplied from the transmission lines to a ground. A current to voltage conversion circuit converts current passing through the transmission lines into a voltage signal. Another current to voltage conversion circuit converts current passing through another transmission lines into a voltage signal.

Abstract: An evaluation circuit 16 repeats processing in which an output VD thereof is reset, there is obtained repeatedly given times a difference between sampled output voltages Vo of a replica circuit 11R when respective times t1 and t2 have elapsed after a voltage Vi is step-inputted to the replica circuit 11R, and the differences are successively summed. A comparator circuit 20 compares a difference cumulation voltage VD with a reference voltage VS. A bias adjustment circuit 15 steps up the bias currents of the replica circuit 11R and an adjusted circuit 11 at every this given times if VD>VS, and ceases the adjustment if VD<VS.