Abstract: A phase locked loop (PLL) clock divider is provided that, in one implementation, includes a divider and a delay locked loop. The divider is operable to divide a reference clock signal and generate a divided clock signal. The divided clock signal has a different frequency relative to the reference clock signal. The delay locked loop is operable to substantially align the divided clock signal to the reference clock signal.

Abstract: An input and output circuit includes a common input and output node, an abnormal voltage detector and a clock generating circuit. The common input and output node is used as an output node in a normal operation mode and used as an input node in a test operation mode where an abnormal voltage level is inputted to the common input and output node. The abnormal voltage detector generates an abnormal voltage signal based upon a detection of the abnormal voltage level at the common input and output node in the test operation mode. The clock generating circuit outputs a first clock signal to the common input and output node in the normal operation mode and outputs a second clock signal to an external circuit in response to the abnormal voltage signal in the test operation mode. Therefore, time and expenses for testing the input and output circuit may be reduced.

Abstract: The invention relates to a pulse width modulator circuit for generating a reference signal having a desired duty cycle comprising an adjustment unit including at least one storage register and a counter, the storage register being configured for storing values corresponding to the desired duty cycle at least approximately and which are set during a working cycle in the pulse width modulator circuit for generating a reference signal, and the counter setting a cycle count Y indicating how often a stored first value X is read during the working cycle A from the storage register, the value stored in the storage register being variable during the working cycle.

Abstract: A low-power multi-level pulse amplitude modulation (PAM) line driver using variable resistors is disclosed for transmitting digital data over controlled-impedance transmission lines. This invention discloses the design of a multi-level PAM driver for high-speed wireline communication, with up to four times improvement in power efficiency over conventional drivers. Two key requirements for high-speed line drivers are first generating the target voltage level onto the controlled-impedance line, and second being impedance matched to the line itself to eliminate signal reflections from the transmitter back to the line. The driver in accordance with the present invention satisfies both of these requirements at very high power efficiency.

Abstract: A driving network for an emitter-switching circuit comprises a pair of cascode-configured transistors, the one of the bipolar type and the other of the MOS type, and the driving network is of the type comprising a driving block for respective conduction terminals and of said pair of transistors. The driving network (20, 30) further comprises sensor means in the driving block suitable for measuring a voltage to be compared with a reference value in a first comparator block. A negative feedback network between the output of the comparator and the driving block to provides a voltage value to said driving block to bias the conduction terminal of the bipolar transistor of the emitter-switching circuit in order to regulate the storage time thereof.

Abstract: The invention provides a clock generating circuit for generating a spectrum spread clock and carrying out high-speed and accurate phase control of a reference clock signal and an output clock signal, which is composed of compact circuits, and a method for generating the clock. The spectrum spread clock generating circuit 1 is provided with a phase comparator unit 10 that compares the reference clock signal CLKS with the internal clock signal in terms of a phase difference, and outputs a control current IC1 in compliance with the result of comparison; a clock generating unit 20 for generating an output clock signal CLKO; a phase difference signal modulating unit 30 for outputting a control current IC3; and a delay unit 40 for delaying the output clock in compliance with the control current IC3 and outputting the internal clock signal CLKN.

Abstract: A capacitance multiplier includes a cascade of a plurality of current amplifiers with each current amplifier having a respective current gain Ki. In addition, the capacitance multiplier includes a capacitor coupled in parallel across the cascade of current amplifiers. Such a capacitance multiplier occupies a smaller area with higher capacitance gain but with low power consumption.

Abstract: A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.

Abstract: A digital-control phase-composing circuit system has a phase-composing circuit which is supplied with two input clock signals having a phase difference therebetween and a control signal, and which composes an output clock signal having a phase between the phases of the two input clock signals on the basis of weighting through the control signal, a binary comparison circuit which compares the phase of the output clock signal to the phase of a reference clock signal, a first up/down counter which increments or decrements a first count value on the basis of the result of comparison made by the binary phase comparison circuit, outputs the most significant bit of the first count value, and outputs a clock pulse when a carry or a borrow occurs in the first count value, and a second up/down counter which operates on the basis of the clock pulse as an operating clock, increments or decrements a second count value on the basis of the most significant bit of the first count value, and outputs the second count value as

Abstract: The clock generator of this invention saves a buffer memory for the data transfer interface, which has conventionally been required, when using a spectrum spread clock in circuits and devices inside a system. The clock generator can easily be applied as the operational clock in a system, and enhances the performance of the system. In the clock generator, the variable delay circuit controls the phase of the reference clock generated by an oscillator. The delay setting circuit is able to vary the setting of the control voltage to the variable delay circuit at each clock cycle, and modulates the phase of the reference clock. The phase modulation means of the delay setting circuit fluctuates the cycle of the output modulation clock to thereby spread the spectrum.

Abstract: Measure-controlled delay (MCD) circuits are provided for synchronizing an output clock to an input clock. In response to triggering of a measure circuit, sample circuits sample outputs of a measure delay array. Sample reset logic prevents output of the output clock when any of a predetermined one or more of the samples correspond to a particular logic value (i.e., logic “1” or “0”). For example, sample reset logic may prevent an MCD circuit from providing the output clock when a sample taken from the earliest sampling point of the measure delay array corresponds to logic “1.” The MCD circuit may then provide the output clock in response to a subsequent triggering for which a sample taken from the earliest sampling point is logic “0.” Phase error of the output clock is thereby reduced. Clock synchronization circuits with improved response to process, voltage and temperature (PVT) variations are also provided.

Abstract: A charge pump circuit which uses a constant current from a constant current source for charging or discharging a capacitor and which obtains an output voltage by shifting a power supply voltage using a charged voltage of the charged capacitor. With this structure, a large current can be limited and generation of noise can be prevented.

Abstract: Provided are a method and apparatus for reducing the number of power ports equipped with an integrated circuit (IC) apparatus by reducing the number of bus outputs that are simultaneously switched, with the use of a master clock signal and a slave clock signal, which is a variation of the master clock signal. The IC apparatus includes a slave clock signal generator, which receives the master clock signal and generates a slave clock signal for controlling simultaneously switching outputs; and a flipflop circuit, which transmits a signal to an external device in synchronization with the slave clock signal.

Abstract: A method and apparatus for updating the control signal received by a delay chain in a DDR application. A register is used to regulate the control signal to the delay chain. The register only updates the signal at the delay chain when a signal is not passing through the delay chain. Additionally, the present invention is directed to a delay circuit that uses a plurality of PMOS and NMOS transistors connected in parallel to each other and to an inverter that provides the desired delay. The delay provided is achieved by sequentially turning off/on a series of the NMOS/PMOS transistor pairs.

Abstract: A method and apparatus is disclosed for adjusting at least one of a supply voltage and a clocking frequency applied to digital circuitry of a computing device, wherein the digital circuitry comprises a plurality of critical path circuits and a corresponding plurality of propagation delay error circuits. Each propagation delay error circuit generates a propagation delay error signal representing an error in propagation delay for the corresponding critical path circuit. The computing device further comprises a voting circuit for comparing the propagation delay error signals in order to select the largest propagation delay error signal for use in adjusting the at least one of the supply voltage and clocking frequency.

Abstract: A differential type delay cell includes a differential amplifier and first and second output capacitor circuits. The differential amplifier is configured to amplify a differential input signal to generate an amplified differential output signal at a pair of output nodes of the delay cell. The first and second output capacitor circuits are respectively coupled to a different one of the output nodes, and are configured to have a variable capacitance that varies in response to variation in a power supply voltage.

Abstract: A phase shift driver for phase shifting an input clock signal at a first phase to generate an output signal at a second phase without missing subsequent input signals. Input logic circuitry of the phase shift driver may receive an input signal at a first phase. Output logic circuitry of the phase shift driver may generate an output signal at a second phase relative to the input signal. The output signal may be a phase-shifted version of the input signal. A reset control circuit may receive a feedback signal from the output logic circuitry and an intermediate signal from the input logic circuitry and generate a reset signal based on the received feedback and intermediate signals. The reset control circuit may control a pulse width of the reset signal to reset the input logic circuitry within a period of time before the input logic circuitry receives a subsequent input signal.

Abstract: A voltage regulator configured to provide a regulated voltage to a load having a first conductance is provided. The voltage regulator comprises a feedback circuit configured to generate the regulated voltage and a frequency compensation circuit comprising a first MOSFET device having a second conductance. The frequency compensation circuit is configured to operate the first MOSFET device so that the second conductance varies in response to the first conductance of the load.

Abstract: A circuit for voltage level translation with zero static current is disclosed for interfacing devices at one supply voltage with devices at another supply voltage. The translation is achieved by using a modified current mirror circuit such that the current mirror is effectively turned off when the output reaches a steady state condition.

Abstract: An apparatus and a method of controlling and tuning clock phase alignment with a dual loop of a hybrid phase and time domain for clock source synchronization in electronic devices are described. The coarse calibration unit generates a plurality of output signals, the output signals having a plurality of fixed phase intervals therebetween. At least one of the fixed phase intervals is equal to complete 360 degrees which are divided by the number of the output signals to cover the phase range of complete 360 degrees. The first fine calibration unit connected to the coarse calibration unit delays the output signals generated from the coarse calibration unit by coupling a programmable delay circuit to adjust the phase of a feedback signal toward the phase of a reference signal.