Abstract: An embodiment device includes a first MOS transistor and a first resistor in series between first node and second nodes, the first resistor being connected to the second node; a second MOS transistor and a second resistor in series between the first and second nodes, the second resistor being connected to the second node and the gates of the first and second transistors being coupled to each other; an operational amplifier including a first terminal connected to a node of connection of the first resistor to the first transistor, a second terminal, and an output terminal coupled to the gate of the first transistor; and a circuit configured to supply a set point voltage to the second terminal of the amplifier.

Abstract: A load control device for controlling the amount of power delivered to an electrical load (e.g., an LED light source) includes first and second semiconductor switches, a transformer, a capacitor, a controller, and a current sense circuit operable to receive a sense voltage representative of a primary current conducted through a primary winding of the transformer. The primary winding is coupled in series with a semiconductor switch, while a secondary winding is adapted to be operatively coupled to the load. The capacitor is electrically coupled between the junction of the first and second semiconductor switches and the primary winding. The current sense circuit receives a sense voltage and averages the sense voltage when the first semiconductor switch is conductive, so as to generate a load current control signal that is representative of a real component of a load current conducted through the load.

Abstract: A logarithmic amplifier includes a logarithmic current preamplifier circuit and logarithmic amplifier circuit. The logarithmic current preamplifier circuit includes an inverting input terminal, an output terminal, and a first diode. The first diode is coupled between the inverting input terminal of the logarithmic current preamplifier circuit and the output terminal of the logarithmic current preamplifier circuit. The logarithmic amplifier circuit includes an inverting input terminal, an output terminal, and a second diode. The inverting input terminal of the logarithmic amplifier circuit is coupled to the output terminal of the logarithmic current preamplifier circuit. The second diode is coupled between the inverting input terminal of the logarithmic amplifier circuit and the output terminal of the logarithmic amplifier circuit.

Abstract: A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal or an output clock signal. The memory state latch circuit is configured to generate the output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and configured to adjust the output clock signal responsive to the latch output signal. The clock trigger circuit is coupled to the latch circuit or the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.

Abstract: A duty timing detector includes a saw-tooth voltage generator that outputs a saw-tooth voltage in synchronization with a toggle signal repeatedly transitioning between a high level and a low level. A sample block obtains a level of the saw-tooth voltage in synchronization with the toggle signal and outputs the obtained level as a first sample voltage. A hold block stores the first sample voltage in synchronization with the toggle signal and outputs the stored first sample voltage as a second sample voltage. A voltage divider divides the second sample voltage to output a division voltage. A comparator compares the saw-tooth voltage and the division voltage to detect a target timing in each duty of the toggle signal.

Abstract: A double-balanced mixer, including a coupling transformer, a first diode cascade circuit, a second diode cascade circuit, and a first set of coils, is provided. The coupling transformer receives a first input signal and generates at least one set of signals with opposite voltage phases. The first diode cascade circuit is coupled to the coupling transformer, and generates a first node voltage according to a first set of bias voltages. The second diode cascade circuit is coupled to the coupling transformer, and generates a second node voltage according to a second set of bias voltages. The first set of coils is coupled to the first and second diode cascade circuits, receives the first and second node voltages and a second input signal, and generates an output signal. The first node voltage is equal to the second node voltage.

Abstract: A mixer circuit including a mixer, a voltage divider circuit, and an amplifier, is provided. The mixer receives a first input signal, a second input signal, and at least one set of bias voltages, and generates an output signal. A frequency of the output signal is related to a frequency of the first input signal and a frequency of the second input signal. The voltage divider circuit receives the bias voltages and generates a common mode signal at an output end. The amplifier is coupled to the mixer to receive the output signal, and is coupled to the output end of the voltage divider circuit and configured to suppress noise in the output signal, and generate a final output signal.

Abstract: A frequency multiplier includes an input section to receive a quadrature phase input signal having an input frequency, a mixer section coupled to the input section by a common mode node that forms a path for the common mode signal current to flow to the mixer section and magnetically coupled to the common mode node or capacitively coupled to the input section to generate a differential switching voltage at odd multiples of twice the input frequency, which switching voltage is applied to inputs of the mixer section, and an output section magnetically coupled to the mixer section, the output section being configured to generate an output voltage having a dominate frequency and sub-dominate frequencies spaced apart by the first multiple, the dominate frequency of the output voltage being a second multiple of the input frequency, where the second multiple is greater than the first multiple. Various arrangements are provided.

Abstract: A power-on reset signal generating device includes a reference voltage generator, a signal driver, and a stabilization circuit. The reference voltage generator generates a power-on reference voltage based on a voltage level of a power supply voltage. The signal driver drives the power-on reference voltage to generate a power-on reset signal. The stabilization circuit receives the power-on reset signal to keep a voltage level of the power-on reference voltage staying during a predetermined amount of time.

Abstract: A feedback control circuit in an LED driving circuit for driving a plurality of LED strings. Each LED string provides a headroom detecting voltage. The feedback control circuit has a status detecting circuit, a counting circuit and a modulating circuit. The status detecting circuit compares each headroom detecting voltage with a low headroom threshold voltage and a high headroom threshold voltage and generates an up self-status signal and a down self-status signal. The counting circuit counts or keeps unchanged and then generates a counting signal based on the up self-status signal and the down self-status signal. The modulating circuit generates a modulating signal based on the counting signal. And based on the modulating signal, the feedback control circuit generates a feedback control signal to regulate a bias voltage supplying the plurality of LED strings.

Abstract: Provided is a semiconductor device which can operate stably even in the case where a transistor thereof is a depletion transistor. The semiconductor device includes a first transistor for supplying a first potential to a first wiring, a second transistor for supplying a second potential to the first wiring, a third transistor for supplying a third potential at which the first transistor is turned on to a gate of the first transistor and stopping supplying the third potential, a fourth transistor for supplying the second potential to the gate of the first transistor, and a first circuit for generating a second signal obtained by offsetting a first signal. The second signal is input to a gate of the fourth transistor. The potential of a low level of the second signal is lower than the second potential.

Abstract: A power-on-reset (POR) circuit for CMOS logic is operable to transition between a POR_active state and a POR_inactive state and can include: (a) VDD/VT threshold circuitry to provide a Vtp_threshold voltage based on input Vdd and PMOS Vtp, and a Vtn_threshold voltage based on input Vdd and NMOS Vtn; (b) POR transition detect circuitry to provide a POR_transition signal (active/inactive) based on a function (Vtp, Vtn), which is a function of Vtp_threshold and Vtn_threshold; and (c) POR transition control circuitry to provide the POR_state signal (active/inactive) based on the POR_transition signal. For a POR out-of-reset transition, the POR transition detect circuitry to switch the POR_transition signal inactive based on the function (Vtp, Vtn) corresponding to the POR_inactive state, and the POR transition control circuitry, responsive to the POR_transition signal switching to inactive, to initiate a POR out-of-reset delay period, and to signal the POR_inactive state after the POR out-of-reset delay period.

Abstract: A bias circuit includes first and second bipolar transistors, first and second field-effect transistors, and a filter circuit. The first field-effect transistor supplies a bias signal to an amplifier. The filter circuit is connected between a collector terminal of the first bipolar transistor and the ground through a base terminal of the first bipolar transistor. The filter circuit has frequency characteristics for attenuating a high frequency component of an RF signal to be input to the amplifier.

Abstract: An apparatus includes a NMOS transistor having a drain, a first PMOS transistor having a drain connected to the drain of the NMOS transistor, a level shifter having an input and an output, the input of the level shifter being connected to the drain of the NMOS transistor and the drain of the first PMOS transistor, a first digital logic circuit having a drain and a gate, a first inverter having an input connected to the Aoutput of the level shifter and the drain of the first digital logic circuit, and a second digital logic circuit having an output connected to the gate of the first digital logic circuit, at least one condition being set in the apparatus during a read operation.

Abstract: A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the reset-detector. The reset-detector is operable to provide a signal to the POR block to generate a global-reset-signal when VCC decreases below a minimum and remains low for at least a first time. The glitch-detector is operable to provide a glitch-signal to the reset-detector to cause it to provide the signal to the POR block when VCC decreases below the minimum and remains low for at least a second time, where the second time is less than the first. The reset-detector can further include a retention-circuit operable to recall a glitch-signal was received and signal the POR block when VCC is restored. Other embodiments are also disclosed.

Abstract: Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.

Abstract: A switching device includes: a lower switching element, an upper switching element having a source connected to a drain of the lower switching element; a control circuit including a first output part that supplies a driving signal to the lower switching element; a Zener diode having a cathode connected to the first output part; a parallel capacitor connected to the Zener diode in parallel; a resistor connected between an anode of the Zener diode and a gate of the lower switching element; and a gate-side capacitor provided separate from a parasitic capacitance of the lower switching element, having a larger capacitance than the parasitic capacitance of the lower switching element, and connected, outside the lower switching element, between the gate and a source of the lower switching element. The capacitance of the gate-side capacitor is smaller than a capacitance of the parallel capacitor.

Abstract: A semiconductor device may include a bandgap circuit that outputs a reference voltage. The semiconductor device may also include a startup circuit coupled to the bandgap circuit. The startup circuit may connect a voltage source to a node that corresponds to an output of the bandgap circuit in response to the bandgap circuit being initialized. The startup circuit may also disconnect the voltage source from the node in response to the reference voltage being greater than a threshold.

Abstract: Provided is a power amplification circuit that includes: an amplifier that amplifies an input signal and outputs an amplified signal; a first bias circuit that supplies a first bias current or voltage to the amplifier; a second bias circuit that supplies a second bias current or voltage to the amplifier; a first control circuit that controls the first bias current or voltage; and a second control circuit that controls the second bias current or voltage. The current supplying capacity of the first bias circuit is different from the current supplying capacity of the second bias circuit.

Abstract: A memory system includes a connector through which power for the memory system is to be supplied from an external device, a controller, a nonvolatile memory device, a power source circuit connected to the controller and the nonvolatile memory device by power lines through which power is supplied to the controller and the nonvolatile memory device, and a power source control circuit that receives a supply of power from the external device through the connector and supplies the power to the power control circuit. The power source control circuit is configured to detect using a divided voltage of a voltage of the power supplied thereto, that the voltage of the power supplied thereto is higher than a predetermined voltage and interrupt the power supplied to the power control circuit if the voltage of the power supplied thereto is higher than the predetermined voltage.