Abstract: In an example method of trimming a voltage reference circuit, the method includes: setting the circuit to a first temperature; trimming a first resistor (RDEGEN) of a differential amplifier stage of the circuit; and trimming a first resistor (R1) of a scaling amplifier stage of the circuit. The trimming equalizes current flow through the differential amplifier stage and the scaling amplifier stage. The method includes: trimming a second resistor (R2) of the scaling amplifier stage to set an output voltage of the circuit to a target voltage at the first temperature; setting the circuit to a second temperature; and trimming a second resistor (RPTAT) of the differential amplifier stage, a third resistor (R1PTAT) of the scaling amplifier stage, and a fourth resistor (R2PTAT) of the scaling amplifier stage to set the output voltage of the circuit to the target voltage at the second temperature.

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.

Abstract: The frequency detector includes a first impedance circuit and a second impedance circuit. The first impedance circuit has a first terminal for receiving an input signal, and a second terminal for outputting a divisional signal. The second impedance circuit has a first terminal coupled to the second terminal of the first impedance circuit, and a second terminal coupled to a first system voltage terminal. The frequency response of the first impedance circuit is different from a frequency response of the second impedance circuit. The resistance of the first impedance circuit, a resistance of the second impedance circuit, and the divisional signal change with a frequency of the input signal.

Abstract: A highly linear time amplifier with power supply rejection. In a reset stage, the threshold value of an over-threshold detector is used for resetting an output node of an amplifier, to eliminate the impact of power supply voltage changes on the threshold value of the threshold detector. A node capacitor unit is charged under the control of an input clock signal. After completion of charging, the node capacitor unit is discharged under the control of a synchronous clock signal. The time amplification gain only depends on the proportion of the charge and discharge current, and the charging and discharging time are completely linear in principle, which eliminates the nonlinearity of the traditional time amplifier, and reduces the negative impact of threshold change on system performance.

Abstract: According to one embodiment, a bus buffer circuit includes an input buffer circuit that receives an input signal, and outputs a non-inversion input signal and an inversion input signal, a voltage conversion circuit that operates by a second power supply, performs voltage conversion on the non-inversion input signal and the inversion input signal input thereto, and outputs the signals as a voltage-converted non-inversion output signal and a voltage-converted inversion output signal, an output retaining circuit that retains the voltage-converted non-inversion output signal and the voltage-converted inversion output signal at a same potential level when an output enable signal is in a disable state, a determinator that determines whether these signals are at a same potential level, a three-state output buffer circuit that outputs the voltage-converted non-inversion output signal or the voltage-converted inversion output signal from an output terminal, and an output controller that sets the three-state output buf

Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

Abstract: A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and an inverter circuit. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The first switch is coupled between a node and a reference voltage. The second switch is coupled between the control terminal of the first transistor and the node. The input terminal of the inverter circuit is coupled to the control terminal of the first switch. The second capacitor is coupled between the node and the output terminal of the inverter circuit.

Abstract: Switch circuitry including an input terminal (1), said input terminal connected to the base of a first transistor (Q1) via a first resistor (R3), said first transistor being an NPN Bipolar Gate Transistor (Q1), said circuitry further comprising a second resistor (R5) connected between the base of said first transistor (Q1) and ground, and including an output line or terminal (3) connected to the collector of said first transistor (Q1), and wherein the emitter of said first transistor (Q1) is connected to ground (earth), said circuitry further including a second transistor (Q2), said second transistor being a PNP Bipolar Gate Transistor, wherein the collector of said second transistor (Q2) is connected via a third resistor (R8) to the base of said first transistor (Q1), and the emitter of said second transistor (Q2) is connected to said input terminal (1), and wherein the emitter of said second transistor (Q2) is additionally connected to the base of said second transistor (Q2) via a fourth resistor (R11); and

Abstract: A semiconductor device including a plurality of power modules each of which includes a power semiconductor switching element that has a temperature detection diode, and a drive circuit that has an output circuit for switching on and off the power semiconductor switching element, and that outputs a warning signal for calling attention if the value of the forward voltage of the temperature detection diode becomes equal to or smaller than a first reference voltage value, and that outputs a protection operation signal for stopping the on/off operation of the power semiconductor switching element if the value of the forward voltage becomes equal to or smaller than a second reference voltage value smaller than the first reference voltage value. The semiconductor device outputs the logical sum of the warning signals of the individual power modules as an external warning signal.

Abstract: A signal generator with direct digital synthesis and tacking filter to generate an oscillator signal. A digital signal generator generates a digital signal; a digital to analog converter is connected to an output of the digital signal generator and converts the digital signal to an analog signal; a filter is coupled to an output of the DAC and filters the analog signal and generates the oscillator signal; a comparator is coupled to an output of the filter and generates a signal indicating zero crossings of the filter output signal; a digital control unit is coupled to outputs of the digital signal generator and comparator and generates a control signal to tune the filter to track a center frequency of the generated oscillator signal. The control signal is generated based on adjacent samples values from the digital signal generator before and after zero crossings of the filter output signal.

Abstract: A switching arrangement for switching off an electric current with a high slew rate, especially a short-circuit current, includes a main line with a first SCR-arrangement including at least a first SCR and a first reverse conducting diode arranged in parallel to the first SCR, and a first bypass line connected to the main line and arranged in a parallel way to the first SCR-arrangement. The first bypass line includes a second SCR-arrangement comprising at least a second SCR arranged in the same polarity as the first reverse conducting diode. The first bypass line further includes at least one capacitor and a DC-voltage source connected to the capacitor for pre-charging the capacitor.

Abstract: In described examples of a ramp circuit, a first terminal of a capacitor is coupled to a ramp terminal and a second capacitor terminal is coupled to a return terminal. A charge source has an input terminal coupled to a supply terminal and a charge output terminal. A resistor has a first terminal coupled to the return terminal. A first switch is coupled between the ramp terminal and a second terminal of the resistor. A second switch is coupled between the charge output terminal and the ramp terminal.

Abstract: Devices and methods include voltage buses. The devices also include one or more power amplifiers coupled to the voltage bus. Each of the one or more power amplifiers include one or more transistors. The devices also include a model that is configured to emulate leakage from at least one of the one or more transistors. A current mirror with a first transistor coupled to the model and a second transistor coupled to the voltage bus. The current mirror is configure to draw charge from the voltage bus based at least in part on the emulated leakage from the model.

Abstract: High-speed flipflop circuits are disclosed. The flipflop circuit may latch a data input signal or a scan input signal using a first signal, a second signal, a third signal, and a fourth signal generated inside the flipflop circuit, and may output an output signal and an inverted output signal. The flipflop circuit includes a first signal generation circuit configured to generate the first signal; a second signal generation circuit configured to generate the second signal; a third signal generation circuit configured to receive the second signal and generate the third signal; and an output circuit configured to receive the clock signal and the second signal, and output an output signal and an inverted output signal.

Abstract: A capacitive transmitter includes a control circuit configured to generate a data signal by delaying input data and to generate a control signal according to the input data and a delayed signal thereof; a capacitor connected between a first node and a transmission node; a driving circuit configured to receive the data signal and to provide an output signal corresponding to the data signal to the first node; and a bias setting circuit configured to set a transmission voltage at the transmission node according to the control signal.

Abstract: A down-conversion mixer includes a converting-and-mixing circuit and a load circuit. The converting-and-mixing circuit performs voltage to current conversion and mixing with a differential oscillatory voltage signal pair upon a differential input voltage signal pair to generate a differential mixed current signal pair. The load circuit includes two transistors each having a transconductance that varies according to a control voltage, two resistors each decreasing a threshold voltage of a respective one of the transistors, and a resistor-inductor circuit cooperating with the transistors to convert the differential mixed current signal pair into a differential mixed voltage signal pair.

Abstract: A flip-flop includes an input switching circuit configured to output an intermediate signal based on an input signal and at least one of a phase of a clock signal or a phase of an inverted clock signal, the phase of the inverted clock signal being opposite to the phase of the clock signal, and block application of a driving voltage to at least one circuit element of the input switching circuit in response to receiving a reset signal representing a reset operation of the flip-flop, and a latch circuit configured to generate an output signal based on the intermediate signal according to the at least one of the phase of the clock signal or the phase of the inverted clock signal.

Abstract: A bidirectional bipolar transistor switch arrangement, including: a first bipolar transistor and a second bipolar transistor connected in anti-parallel between a first terminal and a second terminal, a resistor connected to the base of the first bipolar transistor and the second bipolar transistor and to a control terminal, a first diode connected with anode to the first terminal, and a second diode connected with anode to the second terminal, the first diode and the second diode being connected via respective cathodes to a supply terminal. The bidirectional bipolar transistor switch arrangement is able to control the power supply within a daisy chain with low drop voltage.

Abstract: An electronic circuit, including a first switching device that contains a first semiconductor material with a first band gap, and a second switching device that is coupled in parallel to the first switching device, and contains a second semiconductor material with a second band gap smaller than the first band gap. Each of the first and second switching devices has a control electrode, and the control electrode of the first switching device is coupled to the control electrode of the second switching device.

Abstract: A counter is provided. A charge distributing circuit includes a first switch, a second switch, a third switch, a fourth switch, a third capacitor and a fourth capacitor. A first terminal of the first switch and a first terminal of the third switch are connected to a first input terminal of an operational amplifier. A second terminal of the first switch is connected to a first terminal of the third capacitor and a first terminal of the fourth switch. A second terminal of the third switch is connected to a first terminal of the fourth capacitor and a first terminal of the second switch. A second terminal of the third capacitor and a second terminal of the fourth capacitor are grounded. A second terminal of the second switch and a second terminal of the fourth switch are coupled to a reference voltage.