Abstract: An operation unit includes a first unit for calculating input data and for outputting an error data indicating an error generated as a result of the calculation by using such a mantissa data at a lower order as has been obtained midway of the calculation but is not used as an output result data; and a second unit for outputting error data of the calculation result data from the first-named error data and error data input accompanying the input data.

Abstract: A programmable array logic cell 60 including a sum-of-products array having a single OR gate 70 for providing a sum signal, and including an XOR gate 80 for combining the sum signal with a product signal provided by an AND gate 78 from selected array input and/or feedback signals. The product signal can be the previous state output signal Q for a JK flip flop configuration, or a forced high or low signal for other configurations for programmable output signal polarity.

Abstract: A condition code producing system for an arithmetic unit which is controlled by a micro program and operate on binary floating point data produces a condition code having a plurality of bits and describing an attribute of the binary floating point data. The condition code producing system comprises: a storing device for storing each bit of the condition code; a device for producing a plurality of detection signals from values of predetermined bits of the binary floating point data. This data is transferred to a bus within the arithmetic unit by a micro instruction which involves a data transfer, where the micro instruction is one of a plurality of micro instructions constituting the micro program. The micro instruction comprises a condition control field constituted by a plurality of bits having values depending on at least precision and data portions of the binary floating point data which is transferred.

Abstract: A filter structure uses multiple discrete filter circuits which are cascaded to provide a multiple tap filter of programmable tap length. In one form, an FIR filter may be implemented wherein each circuit generates partial sum operands which must be added to provide a filter output. The cascaded circuits perform partial addition operations near simultaneously by using a serial addition which is synchronized with a start bit. The number of taps in the filter structure implemented by the cascaded discrete filter circuits is variable and may be programmed with a programmable storage register in each discrete circuit which stores operand data fixing the tap length of each discrete circuit. The multiple filter circuits provide a single filter structure with a large tap length and high sampling rate.

Abstract: A three input binary adder with only a single carry path. First adder circuits receive one bit of each of the three words of the same significance. Second cells which include a carry path are coupled to the first circuits such that one of the bits of lower significance from the first circuits is coupled to one of the cells and the other bit from the first circuit is coupled to the next of the cells along the carry path.

Abstract: An electronic adaptive recognizing device which includes an input store having a number of storage locations for receiving an input signal, and a number of addressable stores each having one or more address lines connected to a number of the input store locations in either a random way or one determined by the input signal. The contents of the input store specify addressable store locations at which words of at least one bit are stored. Structure is provided for deriving a common value based on the words stored at the specified addressable store locations and for calculating a corrected value based on a received value and the common value. An updated value is applied, dependent on the corrected value, to each of the specified addressable store locations so that the common value is adapted to changes in the dependence of the received value on the input signal and so that the device can output an appropriate corrected value for a given input signal.

Abstract: A digital signal processing apparatus with a rate-conversion function has at least two digital filters and a memory. A digital signal stored in the memory is selectively transferred to the at least two digital filters. These digital filters perform a filtering operation in parallel, and the results from each of the digital filters are alternately derived by a multiplexer. Thus, high-speed filtering can be executed. The memory temporarily stores a time-division-multiplexed signal which is sequentially read out of the memory and selectively transferred to the digital filters. Thus, a plurality of digital signals can be filtered by the same digital filters without an increase in hardware elements. Therefore, the digital filter section can be integrated in a single semiconductor chip. A shift register may be used as the memory, whereby a circuit arrangement of the digital filter section can be extremely simplified.

Abstract: A serial-bit digital processing system uses registers and latches to synchronize samples and justify sign-bits. Nominally each processing block in the system includes a sign extend register preceding an arithmetic element and an output register following the arithmetic element. Input registers of one arithmetic element may merge with output registers of the preceding arithmetic element. Ones of the registers include a serially coupled latch which is selectively controlled to pass serial sample bits or to replicate the sign bit. The respective registers are clocked with one of two clock signals having different numbers of pulses per sample period and the length of the respective registers are selected so that at the terminus of each sample period the bits of each sample in the processing system are appropriately justified.

Abstract: A terminal input apparatus includes a portable input device having a data input key and a main device provided with a holder for holding the portable input device therein. The holder has a main device side connector which is to be connected to a connector arranged in the lower portion of the portable input device. The holder is arranged so that the holder can be moved relative to the main device between a storing position (at which the stored portable input device is parallel to the main device) and an extraction position (at which the portable input device insertion opening of the holder is projected toward the operation face of the main device, and the portable input device is inclined relative to the main device).

Abstract: An instruction execution unit receives instructions and, in turn, provides a sequence of control words to specify the sequential processing of the operand data provided with the instruction. A sequencer nominally issues a first sequence of control words corresponding to the instruction. The sequencer includes a sequence selector for selecting a second sequence of control words for issuance by the sequencer. Control logic is provided to determine from the operand data, concurrent with the issuance of at least the first issued control word, whether the operand data is ideal with respect to the instruction, where ideal is defined as the predicted nonoccurence of underflow and overflow conditions. On determining that the operand data is ideal with respect to the instruction, the sequence selector is caused to select the second sequence of control words for issuance.

Abstract: A FIR digital filter consists of fundamental symmetrical circuits connected in cascade which can be extended with respect to the number of filter orders and the number of input signal digits which can be processed. The fundamental circuits are readily implemented as integrated circuits by suitably inserting controllable gates or resettable registers between principal circuit elements. In addition, the same inserted elements facilitate individual tests of the principal circuit elements and conversion of the fundamental circuits between even number and odd number filter orders.

Abstract: An apparatus for breaking the periodicity of the pseudorandom bit stream output from a linear sequence generator. The apparatus includes a ring oscillator which periodically corrupts the sequence of the generator. The level of the supply voltage applied to the logic elements of the ring oscillator is varied over time, thereby altering the oscillator output frequency. In a second embodiment, the temperature of the logic elements of the ring oscillator is varied over time, thereby also altering the oscillator output frequency. A system comprising four of the above-disclosed apparatus having different linear sequences and different corrupting influences, are multiplexed, wherein the multiplexing selection criterion is determined by a logical combination of the four linear sequences.

Abstract: A digital analyzing and synthesizing filter bank in which a digital polyphase network in the analyzing filter bank provides sampling rate reduction by dividing an input signal into M complex sub-band signals, and the sub-band signals are subjected to a further staggered sampling rate reduction of the real and imaginary components thereof. This achieves maximum sampling reduction while permitting aliasing distortions to be compensated in the synthesizing filter bank.

Abstract: An information processing system having a memory for storing instructions and operands, a central processor unit which includes a mechanism for fetching and decoding instructions and operands and a bus connected between the processor unit and memory. An associated floating point unit is coupled to the bus and is responsive to floating point instructions for performing floating point operations. The floating point unit and the central processing unit may perform operations independently of the other or may be synchronized to one another, depending upon the type of instruction. A floating point instruction is determined to be a member of a first group of instructions requiring interlock of operation between the central processor unit and the floating point unit or is determined to be a member of a second group of instructions not requiring interlock of operation.

Abstract: In a vector processor which is for use in combination with a main memory (11) and includes an input selecting arrangement (36), vector registers (21-28), a vector operation arrangement (31-34), and a store register (38). An output selecting circuit is not used on selecting operand vectors from vectors held in the vector registers. Instead, the vector registers are fixedly coupled to the vector operation arrangement to raise speed of operation and to simplify vector instructions. Preferably, vector memories are provided to retain vectors which need not be held in the vector registers and must have been stored in the main memory. In this event, a vector bypassing arrangement is used to bypass a result vector from the vector operation arrangement to one of the vector memories for storage therein as a bypassed vector. The input selecting arrangement is used on moving the bypassed vector to one of the vector registers.

Abstract: An electronic calculator has a program calculation function. The calculator also includes a key for designating substitution of numeral data for variables, a key for designating a variable, and a key for representing an interval of variables in addition to normal numeric keys. When numeral data (e.g., 10) is to be substituted for variables (e.g., A to D and H to K) among certain program variables, an operator designates numeral data "10", variables A to D and H to K with the keys. A control section then starts a substituting operation by storing the numeral data "10" in memory areas of a variable memory defined by addresses corresponding to the variables A to D and H to K. Thus, the numeral data "10" is substituted for the variables A to D and H TO K.

Abstract: A vector operation processing apparatus utilizes a plurality of vector registers in a pipeline computer architecture. The vector registers store ordered data elements which are processed in a pipelined vector operation unit in response to a vector instruction which designates selected ones of the vector registers. An input selection circuit is utilized for writing results of the operation performed by the pipelined vector operation unit into the vector registers which are designated by the vector instruction. A write control device is used for causing the writing operation to be performed exclusively on the plurality of vector registers in response to an indication by the vector instruction.

Abstract: An in line testing device for a circuit calculating discrete Fourier transform as well as a circuit including such a device. The device has a processor for calculating the discrete Fourier transform and a processor effecting in line checking of the calculation of the discrete Fourier transform.

Abstract: An adaptive interference cancelling signal processing system includes N+1 processors for cancelling N interfering auxiliary signals from a primary signal. During a prelook or inactive period of the primary signal when a component of interest is not present in the primary signal, the N+1 processors are configured to produce the N(N+1)/2 correlation coefficients L.sub.ij which enable weights for the auxiliary signals to be determined. The same N+1 processors may be reconfigured to convert these L.sub.ij values to the N weights without requiring matrix inversion. The N+1 processors may be reconfigured to multiply the auxiliary signals by the N weights during an active period of the primary signal when the component of interest is present in the primary signal. These weighted auxiliary signals are combined with the primary signal to provide a modified primary signal from which correlated interference in the auxiliary signals has been cancelled.

Abstract: After performing a floating point addition, it is desired to normalize the sum; that is, shift the most significant digit of the mantissa into the left-most digit location, and adjust the exponent accordingly. Prior art techniques required performing the addition before calculating the number of shifts required. The present technique determines an approximate shift from the addends during addition, resulting in a significant time saving.