Abstract: A mixer controlled, variable passband, finite impulse response filter has a plurality of individual filter function blocks which are cascaded. The filter function of each of the individual filter function blocks is represented by a fixed filter function block having a linear phase response. The junctions between successive filter function blocks form signal taps. The signal from each signal tap is delayed by a compensating delay device so that the signals from each of the plurality of signal taps have the same phase function. Signals from selected signal taps are then combined in a predetermined manner to achieve a desired filter transfer function.

Abstract: For digital signal processing with a transversal filter having a (N-1) stage delay chain which is fed at its input with the digital signal to be processed and is provided with taps, subsum signals are stored which correspond to the N/w consecutive groups of, in each case A.sup.w possible combinations of, in each case, w consecutive, A-value tapped signal elements, where the subsum signals are formed from tapped signal elements which are each assigned to a group and are evaluated in accordance with the relevant filter setting. During each delay stage, in accordance with the relevant N/w actual combinations tapped elements, the associated subsum signals are successively read from a memory and added to one another to form an output signal element. The subsum signals can be iteratively formed in that each of the successively-read subsum signals, combined with a correction value, forms a corrected subsum signal which is stored in place of the read subsum signal as a new subsum signal.

Abstract: In an apparatus for generating an aperiodic waveform having a gradually decaying envelope, a sequence of digital samples representing the magnitude of the waveform at sample points is stored in a memory. The stored digital samples are grouped into at least first and second continuous portions, the second portion including that portion of the sequence in which none of the digital samples has a magnitude exceeding 1/n the magnitude of the largest of the digital samples, where n is an integer greater than unity, each of the digital samples of the second portion being scaled by a factor of n. The memory further stores a code indicating the beginning of the second portion. An address counter develops an address signal for sequentially addressing the stored digital samples and code from the memory in response to clock pulses. When the stored code is addressed, an additional clock pulse is supplied from a code detector to the address counter.

Abstract: Supervisory audio tones received from a mobile telephone unit are converted from analog to digital form. The tone is then converted to a complex number by bifurcating the tone path and multiplying one path by a sine function and the other path by a cosine function. The complex numbers are accumulated and the frequencies where significant power exists is found using the discrete Fourier transform. If the power at an assigned frequency exceeds a threshold, the corresponding supervisory audio tone is declared to have been detected.

Abstract: A digital pattern generator generates various kinds of digital pattern signals. A first memory stores an execution signal, an area control signal and a digital pattern. A program counter generates a first address signal in accordance with the execution signal read from the first memory and a first clock signal, and the first memory is addressed by the first address signal. Thus, the pattern generator operates as a microprogram type generator. A second memory includes a plurality of memory areas each storing a digital pattern, and a capacity of each the memory area corresponds to that of the first memory. When the second memory is addressed by a second address signal from an address counter, the pattern generator operates as a sequential type generator. When the memory area of the second memory is selected by the area control signal read from the first memory and the selected memory area is addressed by the first address signal, the second memory acts as an auxiliary memory of the first memory.