Patents Examined by Long Tran
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Patent number: 8405123Abstract: In a gated diode ESD protection structure, the gate is split into two parts to divide the total reverse voltage between two gate regions.Type: GrantFiled: October 27, 2008Date of Patent: March 26, 2013Assignee: National Semiconductor CorporationInventors: Vladislav Vashchenko, Konstantin G. Korablev
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Patent number: 8399293Abstract: The present invention relates to the field of electronic devices and their associated driver and/or controller integrated circuits and in particular to the mechanical packaging of electronic devices and to the packaging of electronic devices and their associated driver and/or controller integrated circuits.Type: GrantFiled: September 13, 2011Date of Patent: March 19, 2013Assignee: Wafer-Level Packaging Portfolio LLCInventors: Juergen Leib, Hidefumi Yamamoto
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Patent number: 8399795Abstract: This invention relates to a plasma surface modification process (and a corresponding a system) of a solid object (100) comprising creating plasma (104) by a plasma source (106), application of the plasma (104) to at least a part of a surface (314) of the solid object (100), generating ultrasonic high intensity and high power acoustic waves (102) by at least one ultrasonic high intensity and high power acoustic wave generator (101), wherein the ultrasonic acoustic waves are directed to propagate towards said surface (314) of the object (100) so that a laminar boundary layer (313) of a gas or a mixture of gases (500) flow in contact with said solid object (100) is thinned or destructed for at least a part of said surface (314). In this way, the plasma can more efficiently access and influence the surface of the solid object to be treated by the plasma, which speeds the process time up significantly.Type: GrantFiled: May 9, 2008Date of Patent: March 19, 2013Assignees: Force Technology, Technical University of DenmarkInventors: Niels Krebs, Alexander Bardenshtein, Yukihiro Kusano, Henrik Bindslev, Henrik Junge Mortensen
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Patent number: 8399969Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a substrate and a chip disposed over the substrate. A solder layer is disposed between the chip and the substrate. A conductive pad is disposed between the solder layer and the substrate, wherein the conductive pad includes a first portion disposed under the solder layer, a second portion disposed away from the first portion and a connective portion disposed between the first portion and the second portion. The connective portion has a width which is narrower than a width of the first portion along a first direction perpendicular to a second direction extending from the first portion to the connective portion.Type: GrantFiled: July 27, 2010Date of Patent: March 19, 2013Assignee: VisEra Technologies Company LimitedInventors: Kuo-Ching Chang, Wu-Cheng Kuo, Tzu-Han Lin
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Patent number: 8399312Abstract: A radiation-hardened semiconductor structure including an insulator material doped with at least one of a transition metal, a lanthanide, and an actinide, and a semiconductor material located over the insulator material. A semiconductor device including the radiation-hardened semiconductor structure is also disclosed, as are methods of forming the radiation-hardened semiconductor structure and the semiconductor device.Type: GrantFiled: July 27, 2010Date of Patent: March 19, 2013Assignee: Alliant Techsystems Inc.Inventor: John S. Canham
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Patent number: 8399976Abstract: A semiconductor device includes a thermoplastic resin case, a semiconductor chip mounted within the thermoplastic resin case, a metal terminal having a wire bonding surface and an opposing contact surface, and a wire connected between the wire bonding surface and the semiconductor chip. The contact surface of the metal terminal is thermoplastically bonded at an area to the inside of the thermoplastic resin case.Type: GrantFiled: October 8, 2008Date of Patent: March 19, 2013Assignee: Mitsubishi Electric CorporationInventors: Masafumi Matsumoto, Tatsuya Iwasa, Junji Yamada, Masaru Furukawa
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Patent number: 8394684Abstract: Techniques are discloses to apply an external stress onto the source/drain semiconductor fin sidewall areas and latch the same onto the semiconductor fin before releasing the sidewalls for subsequent salicidation and contact formation. In particular, the present disclosure provides methods in which selected portions of a semiconductor are subjected to an amorphizing ion implantation which disorients the crystal structure of the selected portions of the semiconductor fins, relative to portions of the semiconductor fin that is beneath a gate stack and encapsulated with various liners. At least one stress liner is formed and then stress memorization occurs by performing a stress latching annealing. During this anneal, recrystallization of the disoriented crystal structure occurs. The at least one stress liner is removed and thereafter merging of the semiconductor fins in the source/drain regions is performed.Type: GrantFiled: July 22, 2010Date of Patent: March 12, 2013Assignee: International Business Machines CorporationInventors: Sivananda K. Kanakasabapathy, Hemanth Jagannathan, Sanjay Mehta
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Patent number: 8395239Abstract: A semiconductor device includes a substrate having a seal ring region and a circuit region, at least one corner bump disposed in the circuit region, a seal ring structure disposed in the seal ring region, and a connector electrically coupling a metal layer of the seal ring structure to the at least one corner bump. The at least one corner bump is configured to be coupled to a signal ground. A method of fabricating a semiconductor device includes providing a substrate having a seal ring region and a circuit region, providing at least one corner bump in a triangular corner bump zone in the circuit region, providing a seal ring structure in the seal ring region, electrically coupling a metal layer of the seal ring structure to the at least one corner bump, and electrically coupling the at least one corner bump to a signal ground.Type: GrantFiled: October 29, 2010Date of Patent: March 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Chung-Ying Yang
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Patent number: 8395072Abstract: A resistance welding quality determination method comprises: a step of detecting a voltage value applied to a welding electrode of a resistance welding machine; a step of detecting a current value supplied to the welding electrode; a step of calculating a welding resistance value based on the voltage value and the current value; a step of correcting the welding resistance value based on a change amount of a contact resistance value between the work and the welding electrode during welding of a work; and a step of determining welding quality of the work based on a corrected welding resistance value obtained by correcting the welding resistance value.Type: GrantFiled: November 12, 2009Date of Patent: March 12, 2013Assignee: Panasonic EV Energy Co., Ltd.Inventors: Kenichi Suzuki, Yugo Nakagawa
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Patent number: 8395163Abstract: A MOSFET capable of achieving decrease in the number of steps in a manufacturing process and improvement in integration includes an SiC wafer composed of silicon carbide and a source contact electrode arranged in contact with the SiC wafer and containing titanium, aluminum, silicon, and carbon as well as a remaining inevitable impurity. The SiC wafer includes an n+ source region having an n conductivity type and a p+ region having a p conductivity type. Both of the n+ source region and the p+ region are in contact with the source contact electrode. The source contact electrode contains aluminum and titanium in a region including an interface with the SiC wafer.Type: GrantFiled: April 13, 2009Date of Patent: March 12, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventor: Hideto Tamaso
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Patent number: 8395148Abstract: It is an object to provide a highly reliable semiconductor device including a thin film transistor whose electric characteristics are stable. In addition, it is another object to manufacture a highly reliable semiconductor device at low cost with high productivity. In a semiconductor device including a thin film transistor, a semiconductor layer of the thin film transistor is formed with an oxide semiconductor layer to which a metal element is added. As the metal element, at least one of metal elements of iron, nickel, cobalt, copper, gold, manganese, molybdenum, tungsten, niobium, and tantalum is used. In addition, the oxide semiconductor layer contains indium, gallium, and zinc.Type: GrantFiled: November 4, 2009Date of Patent: March 12, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Junichiro Sakata
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Patent number: 8390089Abstract: Provided is a back side illuminated image sensor device. The image sensor device includes a substrate having a front side and a back side opposite the front side. The image sensor also includes a radiation-detection device that is formed in the substrate. The radiation-detection device is operable to detect a radiation wave that enters the substrate through the back side. The image sensor further includes a deep trench isolation feature that is disposed adjacent to the radiation-detection device. The image sensor device further includes a doped layer that at least partially surrounds the deep trench isolation feature in a conformal manner.Type: GrantFiled: July 27, 2010Date of Patent: March 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu-Ying Chen, Chun-Chieh Chuang, Jen-Cheng Liu, Dun-Nian Yaung
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Patent number: 8389316Abstract: A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region.Type: GrantFiled: April 19, 2011Date of Patent: March 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Sen Wang, Chung-Te Lin, Min Cao, Sheng-Jier Yang
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Patent number: 8390093Abstract: A galvanic isolation system provides galvanic isolation in digital transfer integrated circuits by using conductivity modulation of the semiconductor substrate. Modulation of the conductivity of the substrate affects eddy current losses of a (differential) RF inductor that is isolated from the substrate by a sufficient amount of dielectric material, which provides a basis for signal transfer from the modulated substrate to the inductor across the isolation barrier.Type: GrantFiled: September 12, 2011Date of Patent: March 5, 2013Assignee: National Semiconductor CorporationInventors: Peter J. Hopper, Peter Smeys, William French, Andrei Papou, Aditi Dutt Chaudhuri
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Patent number: 8378341Abstract: A semiconductor device of the present invention has a first interconnect layer formed over the semiconductor substrate, and a semiconductor element; the first interconnect layer has an insulating layer, and a first interconnect filled in a surficial portion of the insulating layer; the semiconductor element has a semiconductor layer, a gate insulating film, and a gate electrode; the semiconductor layer is positioned over the first interconnect layer; the gate insulating film is positioned over or below semiconductor layer; and the gate electrode is positioned on the opposite side of the semiconductor layer while placing the gate insulating film in between.Type: GrantFiled: December 14, 2009Date of Patent: February 19, 2013Assignee: Renesas Electronics CorporationInventors: Yoshihiro Hayashi, Naoya Inoue, Kishou Kaneko
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Patent number: 8373177Abstract: An LED light source can include protection members to protect bonding wires. The LED can include a substrate including electrode patterns, a sub mount substrate located on the substrate, at least one flip LED chip mounted on the sub mount substrate and a phosphor rein covering the LED chip. The bonding wires can connect each of the electrode patterns to conductor patterns connecting to electrodes of the LED chip. The protection members can be located so as to surround both sides of the bonding wires. In addition, because each height of the protection members is higher than each maximum height of the bonding wires and is lower than a height of the phosphor resin, the protection members can protect the bonding wires from external pressure while the light flux is not reduced. Thus, the disclosed subject matter can provide a reliable LED light source having a favorable light distribution.Type: GrantFiled: October 12, 2010Date of Patent: February 12, 2013Assignee: Stanley Electric Co., Ltd.Inventors: Hiroshi Kotani, Takahiko Nozaki
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Patent number: 8373230Abstract: Systems and methods are disclosed for fabricating a semiconductor device, includes implanting one or more regions on a semiconductor wafer; performing a layer transfer onto a carrier; and transferring from said carrier to a target wafer.Type: GrantFiled: October 13, 2010Date of Patent: February 12, 2013Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Isreal Beinglass, Jan Lodewijk de Jong, Deepak C. Sekar
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Patent number: 8373259Abstract: A system includes an optical transceiver assembly, including a flip chip connection of a semiconductor die with a photonic transceiver that overhangs a substrate to which it is to be connected. The assembly further includes an alignment pin that is held to the semiconductor die at a micro-engineered structure in the semiconductor die. The alignment pin provides passive alignment of the photonic transceiver with an optical lens that interfaces the photonic transceiver to one or more optical channels.Type: GrantFiled: July 27, 2010Date of Patent: February 12, 2013Assignee: Intel CorporationInventors: Brian H. Kim, Simon S. Lee
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Patent number: 8367555Abstract: Methods for removing a masking material, for example, a photoresist, and electronic devices formed by removing a masking material are presented. For example, a method for removing a masking material includes contacting the masking material with a solution comprising cerium. The cerium may be comprised in a salt. The salt may be cerium ammonium nitrate.Type: GrantFiled: December 11, 2009Date of Patent: February 5, 2013Assignees: International Business Machines Corporation, Advanced Technology Materials, Inc.Inventors: Ali Afzali-Ardakani, Emanuel Israel Cooper, Mahmoud Khojasteh, Ronald W. Nunes, George Gabriel Totir
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Patent number: 8368085Abstract: A semiconductor package includes at least four lead frames each having an extending portion and a connecting portion, a heat dissipation plate having a top surface and a bottom surface, at least one semiconductor chip positioned on the top surface of the heat dissipation plate. At least one conductive wire electrically connects the chip to the lead frames. An encapsulation covers the lead frames, the heat dissipation plate, the semiconductor chip, and the conductive wires, while the bottom surface of the heat dissipation plate and the extending portions of the lead frames are exposed.Type: GrantFiled: October 12, 2010Date of Patent: February 5, 2013Assignee: Advanced Optoelectronic Technology, Inc.Inventors: Hung-Chin Lin, Kuo-Fu Peng, Chien-Min Chen, Ko-Wei Chien