Abstract: A communication network utilizing Power Over Ethernet technology including Power Sourcing Equipment (PSE) that includes a multi-purpose device that operates as a current sensing resistor under normal electrical operating conditions and operates as a protection device, e.g., a fuse, under fault conditions, such as, an internal switch failure and an overload occurring simultaneously.

Abstract: One or more derived timers based on a source timer are provided to accommodate a plurality of periodic tasks while maintaining the high resolution of the source timer. To accommodate a number of periodic tasks, a number of derived timers can be selected utilizing a novel method based on the number of periodic tasks that are most time-critical, the number of tasks that are less time-critical, and the number of tasks that can be performed during the source timer interval. The interval and start time for each derived timer is selected based the source timer and number of the derived timer. After establishing the derived timers, the most time-critical tasks can be assigned to the source timer and the less time-critical tasks arranged amongst the derived timers.

Abstract: A method and a system for synchronizing at least two users are described, each user to be synchronized containing its own timer, and the users being connected by at least one communications link, at least one event being transmitted for synchronization on the communications link, a first user determining a first view of the global time as a function of the event, and the at least one second user determining a second view of the global time as a function of the event, the minimum of the first and second views of the global time being transmitted through the corresponding users on the communications link, and each user to be synchronized determining an overall global time from the minimum of a first global time view and a second global time view, and the timer contained therein being synchronized with the overall global time.

Abstract: A present invention provides a PDA with a built-in current limiting device. When powered by a battery, the PDA outputs a current to an external device, wherein the current is within a first current range. When powered by external power through an adapter, the PDA outputs the current to the external device, wherein the current is within a second current range. The first current range is smaller than the second current range. Additionally, a current limiting device built into a PDA is disclosed.

Abstract: Disclosed is an apparatus which places computer program instructions into instruction channels in accordance with predefined criteria such that at least some external event instructions are placed in a special “blocking channel.” The number of instructions, in a channel, is monitored in channel specific counters. When a computer processor is awaiting a response from an external entity event (in other words, is blocked from proceeding with the operation the PU is attempting), as signified by the blocking counter being at a predetermined value, the entire PU or at least processor auxiliary components that would be idle, such as math logic, while awaiting an external event response, are deactivated to save power until an awaited external event response is received.

Abstract: A method and device for reducing an amount of power consumed by a USB device (such as a host/hub/peripheral device which may include a receiver, phy, synchronizer, or other component associated with a data path) adapted to communicate using one or more USB signals each having a synchronization field. In this example, the method may include measuring a length of the synchronization field; associating a power down level for an idle mode based in part on the measuring operation; and disabling one or more portions of the receiver when the USB bus is inactive and/or when the USB device is transmitting data. In this manner, the one or more portions of the receiver are disabled (i.e., powered off or placed in a low power standby mode) during a times when the bus is idle or when transmitting, which can reduce the total amount of power consumed by the USB device.

Abstract: Guardrail installation designs are described that incorporate a box beam rail as the structural rail member. The box beam rail member may have an open cross-section or a closed cross-section. An impact head is provided to bend and deflect the rail member during an end-on collision, allowing the rail member to be deflected away from the roadway and out of the path of an end-on impacting vehicle. The impact head includes a striking face and a chute portion that receives the box beam rail member therewithin. In addition to bending and deflecting the rail member, the impact head may also include a flattening section for flattening the rail member.

Abstract: Power is conserved in a data processing system that includes a processor core and system circuitry coupled to the processor core. A first method for conserving power includes entering a low power state by the processor and the system circuitry and enabling bus arbitration by the processor while the processor core remains in the low power state. One embodiment further contemplates a method of conserving power by granting bus access to a requesting device and entering a power conservation mode by the processor core in response thereto. Bus operations are then performed while the processor core remains in the power conservation mode. Another embodiment contemplates a method of debugging a data processing system in which a debug state is entered by the processor and the system circuitry and, thereafter, bus arbitration is enabled by the processor while the processor core remains in the debug state.

Abstract: A machine code builder providing improved software controlled power management is described. A machine code builder reads pre-executable code and builds machine code from the pre-executable code to maximize a duration that a resource is not required. The resource(s) not required may be user defined or the builder can analyze the pre-executable code to determine which resource(s) are not required. The builder re-organizes machine code to maximize the time a particular resource is not used. Mechanisms are also provided to have resource emulation code execute during re-energizing of a resource to prevent loss of performance.

Abstract: A data processing apparatus comprises a data processing module, which can be operated in a first operating mode with a normal power consumption and a second operating mode, wherein a power consumption of the data processing module in the second operating mode is smaller than the first power consumption or equal to 0. The data processing apparatus further comprises means for signaling a possibility that the data processing module can be placed into the second operating mode, means for providing a time-varying control signal, means for placing the data processing module from one data operating mode to the other, wherein means for placing is formed to place the data processing module into the other operating mode, when means for signaling signals the possibility and the control signal fulfills a predetermined condition.

Abstract: A method for placing a device in a selected mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first user-controlled time window. A device is also described that includes means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input. The selected operating mode may be a reduced power consumption mode, for example, or another operating mode of the device, such as a daisy-chain mode of operation, or a mode that accommodates programming of analog input range.

Abstract: A computing system comprises multiple domains, each having an independent boot process. This boot process involves the selection of one boot option from a list of potentially multiple boot options available to the domain. The apparatus further comprises a centralized configuration utility, and a boot controller within each domain. The boot controller supplies said configuration utility with the list of boot options available to that domain. The configuration utility allows a user to specify en bloc the boot option for multiple domains. This information is then passed back to the boot controllers of the respective domains, which then boot in accordance with the boot option specified by said configuration utility.

Abstract: A transmitting device and a receiving device are coupled together via an interconnect. An electrical idle ordered set is received at the receiving device power management unit after having been transmitted by the transmitting device and received at the input pins of the receiving device and moving through the receiver logic pipeline. At the time the electrical idle ordered set has been recognized at the end of the receiver logic pipeline, the power management unit checks for activity on the interconnect. If there is no activity on the interconnect, then the power management unit causes the receiving device to enter a low power state where the receiver circuitry (input buffers) is turned off. If there is activity on the interconnect when the electrical idle ordered set is received at the power management unit, then the power management unit does not cause the receiver circuitry to be turned off.

Abstract: Methods and systems for managing power and energy expenditures in cores of a processor to balance performance with power and energy dissipation are disclosed. Embodiments may include pre-decoder(s) between levels of cache or between main memory and a level of cache to monitor core execution rates by associating power tokens with each instruction. The power tokens include values representing the average power dissipated by the core for instructions and a sum of the power tokens may be compared with a state of management control bits for performance, energy, and power, to determine whether to increase or decrease power dissipation in the core. The power dissipation is varied by, e.g., adjusting the issue rate of instructions, adjusting the execution rate of instructions, turning off unused units within the core, controlling the frequency and voltage of the core, and switching tasks between cores.

Abstract: A computer data bus interface control selectively connects a computer data bus to functional components of a circuit board or isolates the bus from the functional components. The bus interface control also selectively provides pull-up voltage to the bus, as needed. The connection selection and the pull-up voltage selection can be made, for example, based on whether the board is installed in a system slot or a peripheral slot of the bus.

Abstract: One embodiment of the present invention provides a system that facilitates selectively increasing the operating frequency of an electronic circuit, such as a computer system. The system begins by operating in a low-power state with the frequency and voltage of the electronic circuit set to low levels. Upon recognizing the need for performance beyond the low power level, the electronic circuit enters the first-intermediate power state. In this first-intermediate power state, the frequency and voltage are set to first-intermediate levels. Upon recognizing the need for performance beyond the first-intermediate power state, the electronic circuit enters the maximum-sustainable power state. In this power state, the frequency and voltage are set to maximum sustainable levels. Upon recognizing the need for performance beyond the maximum-sustainable power state, the electronic circuit temporarily enters a boosted power state beyond the maximum-sustainable power state.

Abstract: Timers of a plurality of slave units are synchronized with a timer of a master unit by a) sending a synchronization message on the first network by the master unit, which contains a time measurement of the master unit and a time scale, to the slave units; b) at each slave unit, forming the difference between a time measurement recorded in the slave unit and the time measurement received by the master unit, and correcting the current time measurement of the slave unit by this difference, and, at each unit, the recording of a time measurement upon receipt of the time scale; c) at the master unit, inserting the recorded time measurement into a subsequent synchronization message.

Abstract: A method, apparatus, and computer instructions in a data processing system for managing clocks. The functionality of clock sources in the data processing system is verified to identify a set of valid clock sources in response to beginning an initial load process. Hardware is initialized in the data processing system using a valid clock source from the set of valid clock sources.

Abstract: A method, apparatus, and program storage device for providing clocks to multiple frequency domains using a single input clock of variable frequency. Independent clock signals are generated at predetermined clock frequency targets in response to control signals that are based on a determined bus clock frequency.

Abstract: Control of a loop of a fiber-channel arbitrated-loop serial communications channel is maintained (i.e., the loop connection is held open) as long as a minimum amount of data, which optionally is determined by programming (called a “programmable amount of data”), is available for transmission, in order to reduce the overall amount of time spent arbitrating for control of the loop. The improved communications channel system includes a channel node having one or more ports, each port supporting a fiber-channel arbitrated-loop serial communications channel loop, wherein each port arbitrates for control of that port's attached channel loop. The system also includes an arbitration-and-control apparatus to reduce arbitrated-loop overhead, wherein control of the channel loop, once control is achieved by arbitration, is maintained by the arbitration-and-control apparatus as long as a predetermined amount of data is available within control of the node.