Abstract: A power supplying apparatus having a power saving function and a method of supplying power with a power saving function. An auxiliary power generator generates auxiliary power in response to a cutoff signal. A main power generator senses the generation of the auxiliary power and generates main power in response to the sensed result and a first state of a control signal supplied by a set which performs an intrinsic function. Absent the power cutoff signal, the set performs the intrinsic function in response to the main power and stands by to perform the intrinsic function in response to the auxiliary power. A second state of the control signal places the power supplying apparatus in a power saving mode during which the set may communicate with another circuit. If the cutoff signal is supplied during performance of the intrinsic function, main power is sustained until the intrinsic function is completed.

Abstract: A method of responding to a thermal trip signal generated by a processor of a system having multiple processor nodes. If a processor overheats beyond a critical temperature, a temperature monitor receives the thermal trip signal, and turns off an enable signal to a voltage control module that control power to the processors. The temperature monitor also triggers a system reset. Upon reset, the temperature monitor ensures that all nodes, other than the node with the overheated processor, return to an operational state.

Abstract: Systems and techniques described herein may include both memory mapped and non-memory mapped firmware. A memory region may be in communication with at least one of the memory mapped non-volatile memory region. The memory region may be a cache memory region, and a paging mechanism may be implemented in at least a portion of the cache memory.

Abstract: When controlling a clock to a central processing unit, it is naturally preferable not to change existing circuits which are not related to the control of the clock. A clock control circuit inputs a clock input CLK, and generates a clock output CLKOUT for the central processing unit. In the clock control circuit, CLK is masked by a write operation to an internal register. CLKOUT is stopped by the mask operation. The mask operation is carefully designed to be initiated when the internal cycle of the central processing unit is detected. The resumption of the clock is initiated by interrupts.

Abstract: Clock data recovery (CDR) circuitry or phase locked loop (PLL) circuitry can be provided with a dynamically adjustable bandwidth. One CDR circuit or PLL circuit can be provided to support multiple systems or protocols, multiple parameter requirements for a given system or protocol, and changes in the input frequency or data rate within a given system or protocol. The parameters can include jitter (e.g., jitter tolerance, jitter transfer, jitter generation), source of dominant noise, and lock time. Control signals can be used to dynamically adjust the bandwidth of the CDR circuitry or PLL circuitry while the circuitry is processing data. The control signals can be set by a PLD, by a processor, by circuitry external to the PLD, or by user input.

Abstract: A clock for a computing system. The clock includes a first pulse shaver and a first pin connected to the first pulse shaver. The first pin selectively enables the first pulse shaver to reduce the width of enabling pulses in a clock signal passing through the first pulse shaver. A method for synchronizing data flow in a computing system. The method includes generating pulses; selectively reducing the width of the pulses; and delivering the pulses to a memory element.

Abstract: A low-pass filter in a read channel, having an adjustable cutoff frequency has a low-pass filter 14, a time measuring circuit 15, a storage computing circuit 19 and a current supply circuit 18. The time measuring circuit 15 computes the pulse number of a reference clocking signal. The storage computing circuit 19 obtains the mean value of first and second set values that correspond to current values of the control current when the pulse number of the reference clocking signal increases by 1, and the current supply circuit 18 supplies a control current equivalent to the mean value to the low-pass filter 14. Therefore, even if the same pulse number is computed more than once, the desired current set value can be obtained from the mean value of the first and the second set values, and a control current amount that corresponds to said current set value can be supplied.

Abstract: A frequency manager automatically selects a clock frequency for each device or bus, or for a plurality of devices or buses, in a system, based on various factors and objectives. These factors and objectives can include optimizing performance of the devices without exceeding the system's power/thermal budget. The frequency manager can then control circuits that generate and provide clock signals having the selected frequency(ies) to these devices or buses. For example, in a system that is less than fully populated with devices, embodiments of the invention can select higher clock frequencies than a fully populated system would utilize. Some embodiments of the invention select higher clock frequencies for high-bandwidth devices than for low-bandwidth devices. Other embodiments use information about application programs that will be executed by systems, such as which devices these application programs will frequently access, to select higher clock frequencies for the frequently accessed devices.

Abstract: A system, method, and computer program product are disclosed for executing a reliable warm reboot of one of multiple partitions included in a logically partitioned data processing system. The data processing system includes partition hardware. A request to reboot a particular partition is received within the partition where the particular partition includes multiple processors. Prior to executing the reboot request, the partition hardware is set to a predetermined state. The reboot request is then executed within the particular partition. The predetermined state is preferably achieved by resetting the partition hardware to a predetermined state.

Abstract: A secure boot environment may be provided that includes a secure memory isolated but accessible to a coupled processing device. The secure memory may store and provide boot strap instruction to the processing device. In addition, a authentication system may be provided to ensure secure access to the secure memory.

Abstract: A means for minimizing time for a system/device initial program load (IPL) in a system that will not support instruction prefetching when executing IPL code out of non-volatile memory. The IPL code is organized into a first portion and second portion. The first portion is executed from the non-volatile memory device to configure system memory; the first portion also provides initial control of cache inhibit and cache enable by way of software control. The cache-enabling code is strategically located at a memory page boundary such that the system hardware will disable instruction prefetching in an adjoining page lust past this cache enabling software code. After the first portion of IPL code configures system memory, the second portion is copied into memory through the L2 cache and executed from memory with cache enabled to allow speculative instruction prefetching.

Abstract: A server for carrying out synchronization control, includes (a) at least one event receiver for receiving an event, (b) a memory storing therein distribution schedule information including a plurality of schedule data therein, each of the schedule data including (b1) a timing at which a channel driver controls a media server, (b2) a content of how the channel driver controls the media server, and (b3) a timing type indicating which one of a time and the event the timing is defined by, and (c) a controller which detects whether a timing is established for each of the schedule data included in the distribution schedule information, and transmits a signal to the channel driver, the signal being indicative of a control associated with the established timing.

Abstract: A technique includes receiving an indication of a thermal event in a processor. The processor is part of a computer system. In response to the indication, the processor is powered down, and subsequent to the powering down of the processor, other components of the computer are powered down.

Abstract: Methods and apparatuses for dynamically loading and unloading power management code at runtime in a secure environment are described herein. In one embodiment, exemplary method includes loading authenticated/trusted power management code into a memory of a secure environment of an operating system (OS) and executing the power management code within the secure environment of the OS to handle power management tasks. Other methods and apparatuses are also described.

Abstract: The present invention registers execution modules in association with operating speed attribute data by analyzing code containing operating speed of each of the execution modules as attribute data, groups the registered execution modules by operating speed based on the associated operating speed attribute data and creates a file header containing attributes of each group, upon loading an executable file containing said file header into memory at the time of execution; associates the operating speed attribute data with an address range of the loading for each execution module in the executable file, and controls the operating speed of the processor executing an execution module according to the operating speed attribute data associated with the address of the execution module when the module is executed.

Abstract: A distributed power management system for a bus architecture or similar communications network. The system supports multiple low power states and defines entry and exit procedures for maximizing energy savings and communication speed.

Abstract: Provided with a switching power supply including a built-in chip set so as to control a built cooling fan and or an ambient cooling fan to operate even after the computer system is shut down. As such, the heat built-up within the computer system can be effectively dissipated so as to prolong the service life of the computer.

Abstract: Power is conserved by dynamically applying clocks to execution units in a pipeline of a microprocessor. A clock to an execution unit is applied only when an instruction to the execution unit is valid. At other times when the execution unit needs not to be operational, the clock is not applied to the execution unit. In a preferred embodiment of the invention, a dynamic clock-control unit is used to provide a control signal to a local clock buffer providing a local clock to an execution unit.

Abstract: A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e.g., from internal device logic) is output from the data I/O device to the at least one port.

Abstract: A data path includes a downstream stage that strobes data at an input thereof responsive to a first control signal, an upstream stage that sends data to the input of the downstream stage responsive to a second control signal, and a control circuit operative to fix timing of the second control signal to timing of the first control signal. The data path may further include a second upstream stage that sends data to an input of the first upstream stage responsive to a third control signal having a timing with respect to the second control signal that varies responsive to a frequency at which data is transferred along the data path. A fixed delay circuit, e.g., a fixed delay circuit in a forward path of a DLL or PLL, may generate the first control signal from the second control signal.