Abstract: Integrated circuit devices including standard cells are provided. The standard cells may include a first vertical field effect transistor (VFET) including a first channel region and having a first conductivity type and a second VFET including a second channel region and having a second conductivity type that is different from the first conductivity type. Each of the first channel region and the second channel region may extend longitudinally in a first horizontal direction, and the first channel region may be spaced apart from the second channel region in a second horizontal direction that is perpendicular to the first horizontal direction.

Abstract: A semiconductor device including a substrate including first and second regions, a first transistor on the first region and including a first semiconductor pattern protruding from the first region; a first gate structure covering an upper surface and sidewall of the first semiconductor pattern; first source/drain layers on the first semiconductor pattern at opposite sides of the first gate structure, upper surfaces of the first source/drain layers being closer to the substrate than an uppermost surface of the first gate structure; and a second transistor on the second region and including a second semiconductor pattern protruding from the second region; a second gate structure covering a sidewall of the second semiconductor pattern; and a second source/drain layer under the second semiconductor pattern; and a third source/drain layer on the second semiconductor pattern, wherein the upper surface of the first region is lower than the upper surface of the second region.

Abstract: An embodiment of the present invention provides a display device including: a substrate including a display area in which an image is displayed and a non-display area disposed outside the display area; a pad portion disposed in the non-display area on the substrate and including a plurality of pads spaced apart by a predetermined distance; and a flexible printed circuit board bonded to the pad portion, wherein the flexible printed circuit board may include a plurality of leads, each of the plurality of pads may be bonded to each of the plurality of leads, each of the plurality of pads may include a contact pad electrode that contacts each of the plurality of leads, and the contact pad electrode may include a dummy electrode surrounding an edge of a lower surface of each of the plurality of leads.

Abstract: A method of manufacturing a die seal ring including the following steps is provided. A dielectric layer is formed on a substrate. Conductive layers stacked on the substrate are formed in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is formed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is formed between a sidewall of the second conductive portion and the dielectric layer.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a spacer adjacent to the gate structure, forming a recess adjacent to the spacer, trimming part of the spacer, and then forming an epitaxial layer in the recess. Preferably, the semiconductor device includes a first protrusion adjacent to one side of the epitaxial layer and a second protrusion adjacent to another side of the epitaxial layer, the first protrusion includes a V-shape under the spacer and an angle included by the V-shape is greater than 30 degrees and less than 90 degrees.

Abstract: A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. The mesa has a channel region between a first side and second side of the mesa. A first gate is on a first side of the mesa, the first gate comprising a first gate insulator and a first gate conductor comprising graphene overlying the first gate insulator. The gate conductor may comprise graphene in one or more monolayers. Also disclosed are a method for fabricating the semiconductor device structure; an array of vertical transistor devices, including semiconductor devices having the structure disclosed; and a method for fabricating the array of vertical transistor devices.

Abstract: A film having filling capability is deposited by forming a viscous polymer in a gas phase by striking an Ar, He, or N2 plasma in a chamber filled with a volatile hydrocarbon precursor that can be polymerized within certain parameter ranges which define mainly partial pressure of precursor during a plasma strike, and wafer temperature.

Abstract: A method of implanting an implant species into a substrate at different depths is described. The method includes forming an implant mask over the substrate. The implant mask includes a first implant zone designed as an opening and a second implant zone designed as a block array. The implant species is implanted through the implant mask under an implant angle tilted against a block plane, such that a first implant area is formed by the implant species at a first depth in the substrate beneath the first implant zone and a second implant area is formed by the implant species at a second depth in the substrate beneath the second implant zone. The first depth is greater than the second depth.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to floating-gate devices and methods of manufacture. The structure includes: a gate structure comprising a gate dielectric material and a gate electrode; and a vertically stacked capacitor over and in electrical connection to the gate electrode.

Abstract: Embodiments of the disclosure provide a floating gate memory cell, including: a silicon-on-insulator (SOI) substrate, the SOI substrate including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, and a semiconductor layer formed on the buried oxide layer; a memory device, including: a control gate formed in the semiconductor layer of the SOI substrate; an insulating layer formed on the control gate; and a floating gate formed on the insulating layer; and a transistor device electrically connected to the memory device. The transistor device includes an active region formed in the semiconductor layer of the SOI substrate.

Abstract: A semiconductor device and a semiconductor package including the same are provided. The semiconductor device includes a semiconductor element; a protective layer disposed adjacent to the surface of the semiconductor element, the protective layer defining an opening to expose the semiconductor element; a first bump disposed on the semiconductor element; and a second bump disposed onto the surface of the protective layer. The first bump has a larger cross-section surface area than the second bump.

Abstract: The present disclosure provides a memory and a method for forming the memory. The memory includes: a substrate including a first storage area and a second storage area; a source region disposed in the substrate between the first storage area and the second storage area; a first drain region and a second drain region in the substrate on both sides of the first storage area and the second storage area; a first storage structure disposed on the first storage area, including a first storage unit, a second storage unit, and a first word line gate; and a second storage structure disposed on the second storage area, including a third storage unit, a fourth storage unit, and a second word line gate. The memory can obtain an improved performance.

Abstract: A semiconductor structure for a memory device includes a first gate structure and a second gate structure adjacent to the first gate structure. The second gate structure includes a first layer and a second layer, and the first layer is between the second layer and the first gate structure. The first layer and the second layer include a same semiconductor material and same dopants. The first layer has a first dopant concentration, and the second layer has a second dopant concentration different from the firs dopant concentration.

Abstract: A semiconductor device includes a gate structure disposed on a substrate. The gate structure has a first sidewall and a second sidewall facing the first sidewall. A first impurity region is disposed within an upper portion of the substrate. The first impurity region is spaced apart from the first sidewall. A third impurity region is within the upper portion of the substrate. The third impurity region is spaced apart from the second sidewall. A first trench is disposed within the substrate between the first sidewall and the first impurity region. The first trench is spaced apart from the first sidewall. A first barrier insulation pattern is disposed within the first trench.

Abstract: Embodiments of the disclosure provide a semiconductor device, a semiconductor chip and a method of manufacturing a semiconductor device, wherein the semiconductor device, includes a substrate, a semiconductor layer formed on the substrate, a plurality of gates, drains, and a plurality of sources formed on a side of the semiconductor layer away from the substrate, the gates located between the sources and the drains, and the gates, sources, and drains located in an active region of the semiconductor device, wherein a gate pitch is formed between any two adjacent gates, the formed respective gate pitches include at least two unequal gate pitches, the maximum gate pitch of the respective gate pitches is within a first preset range determined according to a pitch of two gates at the two outermost ends in the semiconductor device in the gate length direction and a total number of gates of the semiconductor device.

Abstract: A semiconductor device includes a substrate including a first region and a second region adjacent to the first region, the first and the second regions being disposed in a first direction parallel to an upper surface of the substrate; an etch-stop layer disposed on the first region and the second region; a separation layer disposed on an upper portion of the etch-stop layer, the separation layer being disposed on the first region; a high-electron-mobility transistor (HEMT) element disposed on an upper portion of the separation layer in a second direction perpendicular to an upper surface of the substrate; a light-emitting element disposed on the second region between the substrate and the etch-stop layer; and a plurality of first insulating patterns covering side surfaces of the HEMT element, the plurality of first insulating patterns extending to the etch-stop layer.

Abstract: A semiconductor structure includes an active region, an isolation structure, a first gate structure, and a second gate structure. The active region is disposed over a semiconductor substrate and has a first portion, a second portion, and a third portion. The third portion is between the first portion and the second portion. A shape of the first portion is different from a shape of the third portion, in a top view. The isolation structure is disposed over the semiconductor substrate and surrounds the active region. The first gate structure is disposed between the first portion and the third portion of the active region. The second gate structure is disposed between the second portion and the third portion of the active region.

Abstract: To allow a metal oxide film composed mainly of O and at least one of Hf and Zr to exhibit ferroelectric properties. After deposition of a hafnium oxide film on a semiconductor substrate via an insulating film, the semiconductor substrate is exposed to microwaves to selectively heat the hafnium oxide film. This makes it possible to form a larger number of orthorhombic crystals in the crystals of the hafnium oxide film. The hafnium oxide film thus obtained can therefore exhibit ferroelectric properties without adding, thereto, an impurity such as Si. This means that the hafnium oxide film having a reverse size effect can be used as a ferroelectric film of a ferroelectric memory cell and contributes to the manufacture of a miniaturized ferroelectric memory cell.

Abstract: A semiconductor device includes: a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region; and a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region. The first active region and the second active region are not fully projected in a vertical direction perpendicular to the substrate.

Abstract: A light emitting diode package including a light emitting diode chip, a phosphor layer disposed to cover an upper portion of the light emitting diode chip, the phosphor layer being configured to convert a wavelength of light emitted from the light emitting diode chip, and a color filter layer disposed to cover an upper portion of the phosphor layer, the color filter being configured to block light having a predetermined wavelength range from being emitted through the phosphor layer.