Patents Examined by Maliheh Malek
-
Patent number: 11456327Abstract: An image sensor includes a semiconductor substrate including a plurality of pixel regions, a first surface, and a second surface opposing the first surface, a plurality of transistors adjacent to the first surface of the semiconductor substrate in each of the plurality of pixel regions, a microlens on the second surface of the semiconductor substrate, and a plurality of conductive patterns in contact with the semiconductor substrate and closer to the second surface of the semiconductor substrate than to the first surface of the semiconductor substrate in each of the plurality of pixel regions.Type: GrantFiled: July 29, 2019Date of Patent: September 27, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young Gu Jin, Young Chan Kim, Yong Hun Kwon, Eung Kyu Lee, Chang Keun Lee, Moo Sup Lim, Tae Sub Jung
-
Patent number: 11437273Abstract: Methods of forming and processing semiconductor devices which utilize a three-color process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing the formation of self-aligned growth pillars. The pillars lead to taller gate heights and increased margins against shorting defects.Type: GrantFiled: February 24, 2020Date of Patent: September 6, 2022Assignee: Micromaterials LLCInventors: Yuriy Shusterman, Madhur Sachan, Susmit Singha Roy, Regina Freed, Sanjay Natarajan
-
Patent number: 11424368Abstract: A transistor having high field-effect mobility is provided. In order that an oxide semiconductor layer through which carriers flow is not in contact with a gate insulating film, a buried channel structure in which the oxide semiconductor layer through which carriers flow is separated from the gate insulating film is employed. Specifically, an oxide semiconductor layer having high conductivity is provided between two oxide semiconductor layers. Further, an impurity element is added to the oxide semiconductor layer in a self-aligned manner so that the resistance of a region in contact with an electrode layer is reduced. Further, the oxide semiconductor layer in contact with the gate insulating layer has a larger thickness than the oxide semiconductor layer having high conductivity.Type: GrantFiled: August 3, 2020Date of Patent: August 23, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
-
Patent number: 11404429Abstract: Three-dimensional (3D) semiconductor memory devices are provided. A 3D semiconductor memory device includes an electrode structure on a substrate. The electrode structure includes gate electrodes stacked on the substrate. The gate electrodes include electrode pad regions. The 3D semiconductor memory device includes a dummy vertical structure penetrating one of the electrode pad regions. The dummy vertical structure includes a dummy vertical semiconductor pattern and a contact pattern extending from a portion of the dummy vertical semiconductor pattern toward the substrate.Type: GrantFiled: August 1, 2019Date of Patent: August 2, 2022Inventors: Younghwan Son, Jeehoon Han
-
Patent number: 11393909Abstract: A semiconductor device comprising a gate electrode on a substrate, a source/drain pattern on the substrate on a side of the gate electrode, and a gate contact plug on the gate electrode are disclosed. The gate contact plug may include a first gate contact segment, and a second gate contact segment that extends in a vertical direction from a top surface of the first gate contact segment. An upper width of the first gate contact segment may be greater than a lower width of the second gate contact segment.Type: GrantFiled: July 17, 2019Date of Patent: July 19, 2022Inventors: Doohyun Lee, Hyun-Seung Song, Yeongchang Roh, Heonjong Shin, Sora You, Yongsik Jeong
-
Patent number: 11387373Abstract: A device wafer is provided that includes a substrate having major and minor surfaces, and a plurality of active devices located at the major surface. A eutectic alloy composition having a first thickness is formed at the minor surface of the substrate. The eutectic alloy composition is partially removed from the minor surface of the substrate such that a second thickness of the eutectic alloy composition remains on the minor surface, the second thickness being less than the first thickness. A bonding layer is deposited over the eutectic alloy composition. The bonding layer is utilized for joining semiconductor components of the device wafer to secondary structures.Type: GrantFiled: July 29, 2019Date of Patent: July 12, 2022Assignee: NXP USA, Inc.Inventors: Colby Greg Rampley, Jeffrey Lynn Weibrecht, Jeremy Kenneth Kramer, Elijah Blue Foster, Melissa Picard
-
Patent number: 11362218Abstract: A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.Type: GrantFiled: June 23, 2020Date of Patent: June 14, 2022Assignee: Silicon Storage Technology, Inc.Inventors: Jinho Kim, Elizabeth Cuevas, Yuri Tkachev, Parviz Ghazavi, Bernard Bertello, Gilles Festes, Bruno Villard, Catherine Decobert, Nhan Do, Jean Francois Thiery
-
Patent number: 11355634Abstract: Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming a first well region and a second well region in the semiconductor substrate; and forming a first gate structure on a surface of the second well region and a portion of a surface of the first well region and a second gate structure on a portion of the first well region. A first opening is formed between the first gate structure and the second gate structure. The method also include forming a sidewall spacer layer covering sidewall and bottom surfaces of the first opening in the first opening; forming a dielectric layer on the semiconductor substrate to cover the first gate structure, the second gate structure and the sidewall spacer layer; and forming a floating plug in the dielectric layer and on the sidewall spacer layer.Type: GrantFiled: January 21, 2020Date of Patent: June 7, 2022Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing: International (Beijing) CorporationInventors: Chun Song, Mingjun Pei
-
Patent number: 11349025Abstract: In some embodiments, the present disclosure relates to a semiconductor device including a semiconductor region over a bulk oxide, which is over a semiconductor substrate. Above the bulk oxide is a lower source region that is laterally spaced from a lower drain region by a lower portion of the semiconductor region. An upper source region is laterally spaced from an upper drain region by an upper portion of the semiconductor region and is vertically spaced from the lower source region and the lower drain region. The upper source region is coupled to the lower source region, and the upper drain region is coupled to the lower drain region. A gate electrode, coupled to the semiconductor substrate and over a gate oxide, is above the upper portion of the semiconductor region. The lower and upper portions of the semiconductor region respectively include a first channel region and a second channel region.Type: GrantFiled: December 20, 2018Date of Patent: May 31, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Hsin-Chih Chiang
-
Patent number: 11349076Abstract: A display panel, an evaporation method of a luminous material, and an equipment are provided. The method is performed by providing an electric field covering an array substrate, and generating luminous material charged particles. After the luminous material charged particles passing through the mask, they will change a direction of motion under an action of the electric field, and move perpendicularly to a pixel area of the array substrate along a direction of the electric field, and then uniformly deposit on the pixel area of the array substrate, which ensures that a uniformity of film formation of the luminous material.Type: GrantFiled: March 5, 2019Date of Patent: May 31, 2022Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.Inventor: Wei Cheng
-
Patent number: 11348871Abstract: Some embodiments include methods of forming integrated assemblies. First conductive structures are formed within an insulative support material and are spaced along a first pitch. Upper regions of the first conductive structures are removed to form first openings extending through the insulative support material and over lower regions of the first conductive structures. Outer lateral peripheries of the first openings are lined with spacer material. The spacer material is configured as tubes having second openings extending therethrough to the lower regions of the first conductive structures. Conductive interconnects are formed within the tubes. Second conductive structures are formed over the spacer material and the conductive interconnects. The second conductive structures are spaced along a second pitch, with the second pitch being less than the first pitch. Some embodiments include integrated assemblies.Type: GrantFiled: January 14, 2020Date of Patent: May 31, 2022Assignee: Micron Technology, Inc.Inventor: Werner Juengling
-
Patent number: 11342414Abstract: A semiconductor device includes a semiconductor layer, a metal layer electrically contacting the semiconductor layer, and a two-dimensional material layer between the semiconductor layer and the metal layer and having a two-dimensional crystal structure.Type: GrantFiled: August 25, 2020Date of Patent: May 24, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Minhyun Lee, Haeryong Kim, Hyeonjin Shin, Seunggeol Nam, Seongjun Park
-
Patent number: 11322564Abstract: A display device capable of reducing a non-display area includes a substrate including at least one hole area disposed within an emission area, and at least one blocking hole passing through inorganic insulating films disposed beneath a light emitting element while including upper and lower insulating films made of different materials. Side surfaces of the upper inorganic insulating film exposed through the blocking hole protrude beyond side surfaces of the lower inorganic insulating film exposed through the blocking hole, respectively. Accordingly, it is possible to minimize a bezel area, which is a non-display area, and to disconnect a light emitting stack by the blocking hole.Type: GrantFiled: October 23, 2019Date of Patent: May 3, 2022Assignee: LG Display Co., Ltd.Inventors: Seok-Woo Son, Jeong-Gi Yun, Jong-Han Park, Jo-Yeon Kim
-
Patent number: 11316077Abstract: A radiation-emitting device includes a semiconductor layer sequence having an active layer that emits a primary radiation during operation, a decoupling surface on a surface of the semiconductor layer sequence, a wavelength conversion layer on a side of the semiconductor layer sequence facing away from the decoupling surface, containing at least one conversion material that converts the primary radiation into secondary radiation, and a mirror layer on the side of the wavelength conversion layer facing away from the semiconductor layer sequence, wherein the at least one conversion material is electrically conductive and/or embedded in an electrically conductive matrix material.Type: GrantFiled: January 25, 2018Date of Patent: April 26, 2022Assignee: OSRAM OLED GmbHInventors: Britta Göötz, Norwin von Malm
-
Patent number: 11309372Abstract: An organic light-emitting diode (OLED) display may have an array of organic light-emitting diode pixels that each have OLED layers interposed between a cathode and an anode. Voltage may be applied to the anode of each pixel to control the magnitude of emitted light. The conductivity of the OLED layers may allow leakage current to pass between neighboring anodes in the display. To reduce leakage current and the accompanying cross-talk in a display, the pixel definition layer may disrupt continuity of the OLED layers. The pixel definition layer may have a steep sidewall, a sidewall with an undercut, or a sidewall surface with a plurality of curves to disrupt continuity of the OLED layers. A control gate that is coupled to a bias voltage and covered by gate dielectric may be used to form an organic thin-film transistor that shuts the leakage current channel between adjacent anodes on the display.Type: GrantFiled: April 27, 2018Date of Patent: April 19, 2022Assignee: Apple Inc.Inventors: Jaein Choi, Andrew Lin, Cheuk Chi Lo, Chun-Yao Huang, Gloria Wong, Hairong Tang, Hitoshi Yamamoto, James E. Pedder, KiBeom Kim, Kwang Ohk Cheon, Lei Yuan, Michael Slootsky, Rui Liu, Steven E. Molesa, Sunggu Kang, Wendi Chang, Chun-Ming Tang, Cheng Chen, Ivan Knez, Enkhamgalan Dorjgotov, Giovanni Carbone, Graham B. Myhre, Jungmin Lee
-
Patent number: 11309433Abstract: A non-volatile memory structure including a substrate, a plurality of charge storage layers, a first dielectric layer, and a control gate is provided. The charge storage layers are located on the substrate. An opening is provided between two adjacent charge storage layers. The first dielectric layer is located on the charge storage layers and on a surface of the opening. A bottom cross-sectional profile of the first dielectric layer located in the opening is a profile that is recessed on both sides. The control gate is located on the first dielectric layer and fills the opening.Type: GrantFiled: March 18, 2020Date of Patent: April 19, 2022Assignee: Winbond Electronics Corp.Inventors: Yi-Hui Chen, Chih-Hao Lin
-
Patent number: 11302827Abstract: The present application discloses a semiconductor device with an oxidized intervention layer and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a tunneling insulating layer disposed over the substrate, a floating gate disposed over the tunnel oxide layer, a lateral oxidized intervention layer disposed over the floating gate, and a control gate disposed over the dielectric layer. The lateral oxidized intervention layer comprises a sidewall portion and a center portion, and the sidewall portion has a greater concentration of oxygen than the center portion.Type: GrantFiled: January 23, 2020Date of Patent: April 12, 2022Assignee: NANYA TECHNOLOGY CORP.Inventor: Te-Yin Chen
-
Patent number: 11302743Abstract: A semiconductor light-emitting device includes a plurality of light-emitting device structures separated from each other and arranged in a matrix form. A pad region at least partially surrounds the plurality of light-emitting device structures. The pad region is disposed outside of the plurality of light-emitting device structures. A partition structure is disposed on a first surface of the plurality of light-emitting device structures and is further disposed between adjacent light-emitting device structures of the plurality of light-emitting device structures. The partition structure defines a plurality of pixel spaces within the plurality of light-emitting device structures. A fluorescent layer is disposed on the first surface of the plurality of light-emitting device structures and fills each of the plurality of pixel spaces.Type: GrantFiled: March 1, 2019Date of Patent: April 12, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Min Kwon, Geun-Woo Ko, Jung-Wook Lee, Jong-Hyun Lee, Pun-Jae Choi
-
Patent number: 11295954Abstract: Polysilicon films (P1,P2) are simultaneously formed on a wafer (W1) and a monitor wafer (W2) under the same growth condition in a wafer process. At least one of a film thickness and phosphorus concentration of the polysilicon film (P2) formed on the monitor wafer (W2) is measured to obtain a measured value. One of a plurality of mask patterns (A,B,C) is selected based on the measured value. The polysilicon film (P1) formed on the wafer (W1) is etched using the selected mask pattern to form the polysilicon resistor (5).Type: GrantFiled: July 4, 2016Date of Patent: April 5, 2022Assignee: Mitsubishi Electric CorporationInventors: Yasushi Takaki, Eisuke Suekawa, Chihiro Tadokoro
-
Patent number: 11295979Abstract: A method of manufacturing a semiconductor device includes: coupling a semiconductor die to a protection layer; forming a first redistribution layer over the semiconductor die, wherein the first redistribution layer includes a first conductive plate of an antenna structure and a first dielectric layer laterally surrounding the first conductive plate; etching the first dielectric layer to form a recess exposing the first conductive plate; filling the recess with a second dielectric material to form an insulating film; and forming a second redistribution layer including a second conductive plate of the antenna structure over the insulating film. The insulating film electrically isolates the first conductive plate from the second conductive plate, wherein one of the first conductive plate and the second conductive plate is configured to radiate or receive electromagnetic wave. The insulating film has a thickness associated with a main resonance frequency of the antenna structure.Type: GrantFiled: July 31, 2020Date of Patent: April 5, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wen-Shiang Liao, Feng Wei Kuo, Chih-Hang Tung, Chen-Hua Yu