Abstract: A radio frequency receiver wherein received signals are directed to a mixer through a pair of signal channels, the bandwidth of one of the pair of signal channels being a selected narrow portion of the bandwidth of the other one of the pair of signal channels. With such arrangement a received signal within a wide band of frequencies is passed to the mixer through both channels to become homodyned to a fixed intermediate frequency signal. Noise received by the wide bandwidth receiver while also passed through the both channels is mixed with only a narrow portion of itself, and hence the amount of noise at the fixed intermediate frequency is reduced with the result that the sensitivity of the receiver is correspondingly increased. An instantaneous frequency measuring unit is also fed by the selected narrow portion of the wide bandwidth signal channel to determine the frequency of the received signal with improved sensitivity.

Abstract: A portable radio used with this invention has two different types of antenna, such as a monopole antenna and a loop antenna. The diversity reception system continuously selects that one of the antenna which provides the better received signal. Antenna selection is performed such that the received signal level is compared with two or more preset threshold levels, and antennas are switched when and only when the received signal level fails to satisfy certain predetermined conditions.

Abstract: A phase-locked loop (PLL) for use in decoding MFM data recordings. The loop uses a counter to generate timing signals which divide bitcells into data and clock windows and which define times within these windows at which transitions in the MFM signal are expected to occur. Data and clock windows of differing relative size are readily accomodated. The PLL has two synchronization modes: one mode allows the PLL to take maximum advantage of both data and clock transitions which occur when reading actual data; a second mode is used during the synchronization period at the beginning of a data block and allows the PLL to lock quickly yet assure that it will lock to the bit frequency and not lock to harmonics or beat frequencies. A charge pump generates the PLL error signal by responding to pump-up and pump-down control signals which are set and cleared in response to the timing signals from the counter and in response to the detection of transitions in the input signal.

Abstract: To avoid long search times for control channels in a radio transmission system, references to other existing control channels, references to a substitute channel allocated to the base radio station and references by the control channel to itself are transmitted by the base radio station at variable time intervals. The content of such references is at least the channel number allocated to the control channel or the substitute channel.

Abstract: The receiver comprises a 90.degree. hybrid and analog-to-digital converters etween the RF section and digital processing; which makes it possible to eliminate a phase correlator, four diode detectors and two differential amplifiers used in previous IFM receivers to obtain the sine and cosine signal samples at an initial time and at a delayed time.

Abstract: To each bit time of a data block, there is associated a counter which is incremented or decremented in accord with the congruence or non-congruence of the c bit sequence associated with the respective counter (for example, the first bit of the c bit sequence). The counters are initialized to an optimum non-zero value and after receiving a number of blocks of data, each containing one sync symbol, the synchronization is determined from the relative content of the counters.

Abstract: An interface unit is disclosed which can make asynchronous data communication between a transmitter unit and a receiver unit. The interface unit includes a shift register for receiving start data designating a start of data input and input data from the transmitter unit. The start data is used as an interruption signal indicating data input to the receiver unit and is used as an inhibition signal for inhibiting clock application to the transmitter unit. The inhibition of clock application is removed by a control signal transferred from the receiver unit to the interface unit. Clock application to the transmitter unit is restarted in response to the control signal, and a next new data is transferred to the interface unit. Thus, the interface unit can easily and smoothly control asynchronous data communication between the transmitter unit and the receiver unit by means of simple circuits.

Abstract: An AGC voltage generating circuit for an AM radio comprises a product detector adapted to receive an IF signal modulated by an AF signal and synchronously detect the AF signal, a low pass filter adapted to derive from the product detector a filtered voltage indicating the average IF signal strength, and a reference voltage generating circuit ratiometrically related to the low pass filter through a common DC power supply and effective to generate high, medium and low reference voltages ratiometrically related to each other with the high and low reference voltages defining a voltage window about the medium reference voltage. Comparator apparatus is effective to compare the filtered voltage from the low pass filter with the high, medium and low reference voltages from the reference voltage generating circuit. Current source apparatus is responsive to the comparator apparatus to control the voltage on a capacitor to maintain the filtered voltage equal to the medium reference voltage.

Abstract: An interface circuit is coupled between the last stage of an FSK receiver and a limiter to provide a biasing voltage signal to the limiter. The receiver includes a power saver circuit which supplies power on an interrupted basis. The interface circuit contains maximum and minimum detectors which derive and hold voltages corresponding to the maximum and minimum values of the discriminated signal from the receiver. These maximum and minimum corresponding voltages are averaged in a predetermined manner to provide the biasing voltage to the limiter. Thus, a proper bias voltage level can be accurately and quickly determined, and supplied to the limiter when power is supplied.

Abstract: A timebase adapted to be synchronized to an external clock comprises at least one generator incorporating a voltage-controlled oscillator adapted to be controlled by the result of comparing an external synchronization signal from an external clock with an output signal of the timebase. Each generator comprises at least one differential comparator receiving the external synchronization signal and the timebase output signal. It drives a summing circuit on the input side of the control input of the oscillator of the generator in question. The generator further comprises a calibration system comprising a threshold detector connected to the output of the phase comparator, a calibration voltage adjustment circuit connected between the threshold detector and a second input of the summing circuit, and a trigger circuit in and controlling the adjustment circuit.

Abstract: This invention pertains to a method and system for transmitting high speed data from a transmitter to a receiver over several low speed data channels. At the receiver end the differences in the transmission times between data channels are detected and the signals from the faster data channels are delayed to insure that the output high speed data stream is correctly assembled. The differences in the transmission times are monitored during data transmission and if a change is detected the transmission is interrupted and retraining is requested.

Abstract: Disclosed is a digital phase-locked loop circuit for telecommunication circuits receiving bipolar codes. The digital phase-locked loop circuit includes a transition timer means for counting a transition duration between a high mark and a low mark in said bipolar code. A clock recovery signal is generated by dividing a transition duration by a value, such as two, to indicate an apparent zero crossing time, and comparing the apparent zero crossing time with the reference clock in the circuit receiving the bipolar code. The reference clock in the receiving circuit is adjusted in response to the clock recovery signal in order to maintain the reference clock substantially in phase with the incoming bipolar code.

Abstract: A receiver is disclosed for acquiring and tracking a data signal in a highly stressed environment. The receiver comprises first and second I.F. sections, a mixer for translation from the first I.F. frequency to the second I.F. frequency, a 2 KHz bandpass filter at the second I.F. frequency, signal translator for synchronous translation of the signal at the second I.F. frequency to baseband, a digitizer for complex sampling operation on the baseband signal, a microprocessor for processing the digital samples, and a numerically controlled oscillator coupled to the mixer and controlled by the microprocessor. The microprocessor formulates matched digital discrete Fourier Transform filters which drive frequency, phase and symbol lock loops at the symbol rate. Each of the loop filters is formed by symbol-rate recursive, first-order equations.

Abstract: A squelch circuit in which a phase locked loop (PLL) (5) having a voltage controlled oscillator (VCO) (7) and a phase comparator (10) is used to detect the number of zero crossings, these being low for a speech signal and high for noise. The error voltage produced in the phase locked loop (5) is fed through a network (12) which ensures that the matching of the input signal to the oscillator is faster when the input frequency drops than when the input frequency rises. The input signal is clipped to enhance the frequency spectra of speech by using a limiting amplifier. The muting gate (2) output is derived from the VCO (7) control voltage of the PLL (5) to mute the output of the receiver when the VCO (7) output frequency is higher than a pre-set frequency for more than a pre-set time.

Abstract: An adaptive timing technique is disclosed for adjusting the sampling times of a received digital signal for fewer regeneration errors. In accordance with the disclosed technique, a sequence of digital signal samples is formed and an error signal is generated by comparing a selected sample in the sequence to a threshold. The sampling times of subsequently formed samples are then altered in response to the sample sequence and error signal only when the sample values in the sequence are successively increasing or decreasing.

Abstract: A programmable time varying attenuator has a reprogrammable digital circuit or impressing an analog attenuation signal on a continuous wave noise signal. This signal is fed to the input of a receiver and since the digital circuitry can be reprogrammed with a known sequence to effect a desired analog attenuation, a receiver's performance can be monitored and evaluated when the attenuated signal or error signal is simultaneously received with information signals. A desired time relationship between the information signals and the time varying attenuating test signal or error signal is maintained since both are slaved to a common standard. The programmable time varying attenuator is programmable independent of the information signal source and, therefore, is adaptable with different sources while being a highly reliable and cost effect device for system testing.

Abstract: An automatic bias control circuit for a data limiter in a synchronous data communications system is disclosed. After word synchronization is achieved, the automatic bias control circuit is enabled and a time relationship between the limited data signal edges and a synchronized local clock signal is detected. The automatically controlled bias level is then modified upward or downward by an additive or subtractive voltage increment for a period of time related to the data bit rate so that the true baseline of the data signal is approximated by the bias level and the detected time relationship is thereby adjusted so that the edges are essentially synchronized with the local clock signal.

Abstract: A clock and carrier recovery circuit, and a related method, for use in a minimum shift keying (MSK) receiver demodulator. The clock and carrier recovery circuit uses ringing filters to lock onto two frequency-doubled tone components of a received MSK signal. A signal having the same frequency as the clock is recovered by taking the difference of the outputs of the two filters. The output of each filter is then combined separately with a signal having a frequency to produce to signals, each having a frequency equal to twice the carrier frequency and having complementary amplitude modulation. These two signals are summed to cancel the amplitude modulation and the resulting sum signal, having constant amplitude and a frequency twice that of the carrier, is divided by two to recover the carrier signal.

Abstract: A system for economically recording information indicating radio stations listened to on a radio is disclosed which analyzes listening habits in a relatively short fundamental time period to determine if within that fundamental time period a particular station was tuned for at least a substantial time period within that fundamental time period. If this criteria is met, the system records the station in a solid state data location. Ratings are determined by the number of data locations each station is stored in over a particular interval.

Abstract: A radio frequency transmission system contains at least one coherently modulated information signal, for example, a T.V. signal. At a transmission, the information signal is combined with two pilot tones, F1 and F2, related by the equation F1=N/M F2, where N and M are integers. The combined signal is suppressed-carrier modulated at microwave frequencies and transmitted to a receiver. At the receiver, the signals are demodulated by a local oscillator. The two pilot tones are then separated from the information signal and are compared to each other. The local oscillator frequency is controlled in response to this comparison such that the pilot tones at the receiver bear the same relationship to each other that they had at the transmitter. When this is achieved, the local oscillator frequency is the same as the suppressed-carrier frequency and co-channel interference is prevented.