Abstract: A direct conversion receiver in which the quadrature I and Q signals are converted into pulse density modulated digital data streams by delta-sigma modulators 14, 15. The resultant digital data streams are then processed in a logic block 18 according to predetermined logic truth tables. The digital output of the processor 18 is then converted back to an analogue signal.

Abstract: A radar warning receiver includes means for distinguishing pulsed or continuous fixed frequency radar signals emanating from a radar transmitter from variable frequency signals such as those radiated from a nearby superhomodyne receiver. This invention includes a superheterodyne receiver having a local oscillator that is repeatedly varied in frequency over a range of frequencies sufficiently large and at a rate fast enough to cause any signals within an input range of frequencies to be detected by a sensitive, limited bandwidth detector. If an input signal is fixed in frequency, that signal will be detected at the same time during successive sweeps of the local oscillator, and a correlated output will be generated; otherwise, an uncorrelated output will be generated. If the number of correlated outputs equal or exceed the uncorrelated outputs detected, then an alarm is provided.

Abstract: Transmission system for bi-phase modulated signals. Generally receiving filters for these signals will have a frequency response up to twice the bit frequency (twice 1/T) passband. For colored noise whose power increases as the frequency increases this may mean a considerable deterioration of the signal-to-noise ratio compared with the signal-to-noise ratio for unmodulated NRZ-signals. In order to increase the signal-to-noise ratio a receiving filter is used in this case, whose frequency response approximates zero above the bit frequency (1/T) (stopband) and which for lower frequencies is determined such that after filtering a predominantly three-level signal is obtained. The binary data signal can be drived from this signal by rectification and slicing. Use: Optical communication systems.

Abstract: A receiver input circuit comprising a control loop for amplification control, wherein the control signal for the control loop is derived from the intermediate frequency signal and supplied to the part of the circuit preceding the mixer stage. The receiver input circuit furthermore comprises a second amplification control loop whose control signal is taken out prior to the mixer stage, and a third amplification control loop whose response threshold and frequency band width are lower than the response threshold and frequency band width of the first and second control circuits.

Abstract: An amplifier for use with a local oscillator in a frequency converter including a mixer for converting a number of channel frequencies received into a certain band of intermediate frequencies, comprises a circuit for amplifying an oscillation signal from the local oscillator and supplying an amplified signal to the mixer through an output terminal thereof, and a trap circuit composed of distributed constant elements for suppressing the certain range of intermediate frequencies. The distributed constant elements include a first microstrip line connected in series to the output terminal, a second microstrip line connected in series with the first microstrip line, and a third microstrip line connected in parallel to the second microstrip line. The second microstrip line serves as an open stub, and the third microstrip line as a short stub.

Abstract: A wide area coverage radio communication system of the type adapted to relay a message substantially simultaneously from a plurality of fixed location sites to a plurality of portable or mobile units includes a plurality of repeaters at each of the sites. Each of the repeaters is arranged to transmit and receive on a respective different frequency duplex pair or channel. Control means at one of the sites senses channel availability at all of the sites and causes one repeater at each of the sites to transmit the message on its respective different frequency. Access to the system by the portable units is provided on a trunked basis through the control means.

Abstract: In FM transmitters, particularly land mobile FM transmitters, wherein a speech signal is pre-emphasized between 300 Hz and 3 kHz, whereafter it is filtered to provide a sharp cut-off and wherein the maximum peak frequency deviation is limited in order to maintain channel integrity, the level of undistorted speech can be raised to within 90% of the transmitter peak deviation by directly connecting an amplitude limiter to a filter amplifier which behaves as a level sensitive filter when the speech signal has been limited and prevents ringing and overshoot from occurring. The output from the filter amplifier is coupled to a low pass filter, typically a fourth-order Butterworth filter, via an attenuator which reduces the amplitude of the signal to prevent the onset of further clipping.

Abstract: Digital Data receiving apparatus includes means for adjusting the timing of the sampling instants. A phase controlled oscillator (PCO 19) provides timing signals for sampling the received signal and is controlled, at the commencement of a received signal, by a timing initialization circuit (17) responsive to repetitive phase alterations in a training sequence. The timing initialization circuit (17) includes a plurality of Discrete Fourier Transform (DFT) circuits (23) responsive to frequencies dependent on the power spectral densities of the received signal, which received signal may be modulated at a normal rate or a fall-back rate. The DFT circuits (23) measure the correlation of locally-generated frequencies with the incoming samples for a predetermined number of such samples to produce a plurality of complex signals. A selector circuit (24) selects a pair of the complex signals dependent on the modulation rate.

Abstract: A sync detect circuit for detecting a sync code in a stream of digital data includes a counter that converts locally generated clock pulses to a plurality of discrete addresses that occur every bit period of time. The addresses are applied to a PROM which upon being addressed provides a sync verify code. The sync verify code is applied to a sync verify detector which provides an enable signal to the address generator if the code compares with the logic levels of a coincident bit in the stream of digital data provided from the PROM and after the full sync code has been rectified a sync detect signal is provided from a sync detector circuit.

Abstract: A circuit for obtaining a clock pulse synchronized to a data signal received at a receiving side, which has a plurality of clock pulses having a repetition frequency equal to that of a clock in a transmission side but being different from one another in phase. On reception of the first data bit of the received data signal, the timing of the first data bit is detected at a detection circuit in reference to the plurality of clock pulses. According to the detected timing, a selector circuit selects one of the plurality of clock pulses with a predetermined constant phase difference from the received data signal.The detection circuit comprises D-type flip-flops, and the selector circuit comprises AND gates.

Abstract: A frequency jump radiocommunications system fixed station in which n receivers and n channels may be connected to p transmitters; p being less than n. A management circuit is provided on each of the n channels to provide signals indicating the active/nonactive state of each channel. A time/frequency law generator is provided on each channel to generate the jumped frequency signals. A general control circuit receives the active/nonactive signals and provides a connection control signal and provides a connection control signal assigning one of the n channels to one of the p transmitters. The general control circuit also generates a transmission authorization signal to authorize the p transmitters to transmit. The connection control signal is received at first and second connection matrices.

Abstract: A compressed single side band communication system and method in which the audio signal is compressed prior to pre-emphasis and thereafter summed with a pilot tone for further compression prior to transmission. Initially, only the pilot tone is transmitted at full rated power to aid in acquisition of the signal by the receiver. Thereafter, the transmitter ALC is disabled and the pilot tone is attenuated. The receiver adjusts the frequency characteristics of the pilot tone filter and phase lock loop filter in the detector as a function of lock-on. The delay after loss of lock-on in reverting to wide band pilot tone and wideband loop filters is varied as a function of signal strength. The pilot tone may be modulated for tone coded squelch. The modulating source is located in the return end of the phase lock loop filter. A unique filter is provided to insure acquisition of the pilot tone.

Abstract: An integrated receiver antenna device comprising a pair of antenna elements providing a spiral antenna for receiving radio frequency signals over a broadband of frequencies with an extended high frequency limit and providing high sensitivity over the broadband of frequencies. The elements each have first and second ends and provide a pair of interwound conductive windings with their first ends positioned proximate to each other at the center of the antenna for providing sensitivity at the high frequency limit of received radio frequency signal, while the second ends of the elements are displaced from the first ends and positioned at the periphery of the antenna. A detector mixer unit is connected between and positioned proximate to the first ends of the antenna elements for deriving radio frequency signals received by the antenna elements and receiving an input signal for providing an oscillating signal at the detector mixer unit for producing an output signal.

Abstract: To convert an input-word sequence into a digital line code of half the bit rate of the input-word sequence, particularly for digital color television signal transmission, an encoder is disclosed which has a difference branch in which the difference (D.sub.i) between every two successive input words (X.sub.i-1, X.sub.i) is converted into a difference code word (D.sub.i) by adaptive PCM quantization, and a sum branch in which the sum (S.sub.i) of the same successive input words (X.sub.i-1, X.sub.i) is converted into a difference code word (S.sub.i +P.sub.i) in a hybrid DPCM encoder. These two words are combined into a line code word (C.sub.i) by an adder (9). The quantizing characteristic of the adaptive PCM quantizer (1) is selected as a function of the prediction error present within the hybrid DPCM encoder (2). The decoder at the receiver of the novel communication system splits up the received line code word (C.sub.i) into the difference code word (D.sub.i) and the sum code word (S.sub.i +P.sub.

Abstract: A programmable circuit is provided for the series-parallel transformation of a digital signal and application thereof to a digital video signal receiver, comprising a circuit for detecting the synchronizing words in the series digital signal, a phase comparator generating pulses I and I characteristic of the coincidences and non coincidences between the parallel clock signal generated by a programmable divider from the series clock signal and pulses characteristic of the times when synchronizing words are detected; a logic circuit receives the pulses from the phase comparator and transfers them to the sync control input of a programmable divider when a predetermined programmable number of successive non coincidences or coincidences has been detected. This logic circuit also has a disconnecting control input. This circuit is implanted in a prediffused integrated network.

Abstract: A PSK integrated circuit modem employs multi-mode filters in its switched capacitor circuitry for providing a plurality of filter response to accomodate a plurality of modem protocols. Each capacitor is selectively connected or disconnected from the circuit by a transistor switch, and selectively connected and disconnected from the circuit voltage reference by a transistor switch. The switches operate out of phase with each other so that when any capacitor is connected in the circuit, it is disconnected from the reference voltage and when any capacitor is disconnected from the circuit, it is connected to the reference voltage. The modem switch minimizes the effect of stray capacitance from the unselected capacitors and their associated transistor switches that have been turned off.

Abstract: A demodulator logic for FSK signals on an RF carrier in a direct conversion radio receiver, wherein the received signals are mixed with a local oscillator to provide quadrature baseband signals, characterized in that the demodulator logic comprises two clocked D-type flip-flops, FF1,FF2 one baseband signal being applied direct to the clock input CK of one flip-flop and inverted to the clock input CK of the other flip-flop, the second baseband signal being applied to the D inputs of both flip-flops, one input Q from one flip-flop being algebraically combined with one output Q from the other flip-flop to provide a demodulator signal output of the receiver, the two flip-flop outputs being chosen so that for a given FSK value they always have the same logic value.

Abstract: Data transmission equipment includes a plurality of data stations connected in series through a loop transmission path. A synchronizing station is connected to the data stations in the loop transmission line. The synchronizing station generates transmission signals made up of a synchronizing slot, an address slot and data transmission slots. A display board for setting and displaying data is connected to at least one of the data stations. Process line controllers are connected to data stations to transmit data related to process control to, or receive data from, a process control apparatus. The data transmission equipment further includes sensor bases connected to data stations. Each data station includes a coupling unit connected in series with the loop transmission line, transmitting and receiving units connected to the coupling unit through a bus, input units provided between the transmitting units and the sensor bases, and a bus provided between the transmitting units and the sensor bases.

Abstract: A phase-locked clock incorporating a combined phase comparator and control device (20) that controls a multiplexer (22). Multiplexer (22) receives as inputs the outputs from circuits called decoders which add a predetermined digital value to, or subtract said value from, the value applied to the inputs thereof, which latter value is received from a buffer register (30) disposed at the output of the multiplexer. The contents of the buffer register are transferred under the control of a local oscillator (10). The output from the buffer register is fed to a fixed frequency divider (13) through a carry logic circuit (32).

Abstract: A data interface circuit for interfacing between an asynchronous data source providing data in start/stop format and a synchronous data communication channel is provided. The data interface circuit has a transmit portion and a receive portion which function independently. Upon receipt of asynchronous data, the transmit portion strips start and stop bits from the data and transmits the data in data frames of variable length characterized by beginning and ending with synchronizing idle codes. The synchronizing idle codes are transmitted in the absence of data to maintain synchronization. A code circuit insures that a data word is never the same as the idle code. Similarly, upon receipt of synchronous data and idle codes, the receive portion stores the data and controllably adds start and stop bits. Data in start/stop format is asynchronously provided at an output of the receive portion.