Abstract: A compiler framework uses a generic "shell" and a generic back end (where the code generator is target-specific). The generic back end provides the functions of optimization, register and memory allocation, and code generation. The code generation function of the back end may be targeted for any of a number of computer architectures. A front end is tailored for each different source language, such as Cobol, Fortran, Pascal, C, C++, etc. The front end scans and parses the source code modules, and generates from them an intermediate language representation of the source code programs expressed in the source code. The intermediate language represents any of the source code languages in a universal manner, so the interface between the front end and back end is of a standard format, and need not be rewritten for each language-specific front end. A feature is a method for doing code generation using code templates in a multipass manner.

Abstract: Disclosed is a decentralized data-processing star network with a contention system having a plurality of terminal devices and a concentrator to interconnect the terminal devices via a transmission medium. Any of the terminal devices can start to transmit a packet immediately after a pause disposed to prohibit all transmissions, the pause occurring every time a packet has been transmitted. The concentrator has a start bit generation device for generating a start bit in accordance with the timing that the terminal devices should transmit their start bits and a relay device for ORing the generated start bit with each bit of a packet modulated as predetermined with a first frequency, converting it into a packet modulated as predetermined with a second frequency, and sending it out.

Abstract: The electronic postage meter includes a printing unit which is responsive to a plurality of motors for printing of a postage indicia in response to a control circuit. The control circuit is comprised of a programmable microprocessor in bus communication with an accounting means having memory units for accounting for the postage printed by the printing unit responsive to the programming of the microprocessor. An integrated circuit includes an address decoding module means for generating a unique combination of ASIC control signals in response to a respective address placed on the bus by the microprocessor. A timer register is responsive to ones of the control signals from the address decoding module to enable writing of the timer data into the timer registers by the microprocessor. The timer unit is responsive to the timer data for timer data. Also included are a plurality of non-volatile memory units.

Abstract: The invention uses a storage device effectively to supply data to as many user terminals as possible. Sub-control units read unit data in which dynamic image data having continuity is divided and compressed from storage devices sequentially according to the tokens stored in queues of a system control unit, and supplies buffers corresponding to storage devices through a change-over switch for connection corresponding to the tokens. The unit data stored in the buffers is supplied to terminals as analog data of dynamic image through expanders and D to A converters. Therefore, the unit data from K units of storage devices to M (K * N) units of terminals at the substantially same time.

Abstract: A physical layer controller for use in a data transmission network is disclosed which includes an automatic scrubbing arrangement that is activated upon the occurrence of a physical layer controller reconfiguration. The transmitter output port as well as each channel output of the physical layer controller has an output dirty flag associated therewith. Similarly, the input port as well as each channel input has an associated input dirty flag. A scrubbing arrangement automatically scrubs certain outputs after a configuration change. More specifically, in the absence of a blocking condition after a configuration change, the scrubbing arrangement will automatically scrub each output which has a new source and one of: 1) its associated output dirty flag is set to a first level; and 2) it is connected to an new source which has its associated input dirty flag set to a first level. In a method aspect, output dirty flags are set for each output that has the potential to transmits a data frame.

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2).times.(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle.

Abstract: An object-oriented hardware configuration system for enabling centralized user configuration of hardware in a computer system includes a plurality of object-oriented hardware interface objects each representing a hardware device physical connector, and a plurality of object-oriented hardware module objects. Each of the hardware module objects represents a hardware device that is user-configurable. Each of the hardware module objects includes one or more hardware interface objects associated with the hardware device such that connectors of the hardware device are defined. An object-oriented hardware configuration object is provided, wherein the hardware configuration object includes a plurality of hardware module objects that represent hardware devices connected to a particular computer system. The hardware configuration object defines a hardware configuration of the particular computer system.

Abstract: This invention generally relates to data management in a data processing and communication station that acts as an interface station between a central or control terminal and a subsystem. The interface station is adapted to receive messages from and to transmit messages to a control station as well as to receive data from and to transmit data to a subsystem. The interface station comprises a memory unit with multiple map locations having an associated descriptor field including a set of one or more flags. The control station transmits messages to the interface station whereby each of the messages is associated with one of the map locations in the memory unit. The interface station checks the states of the flags in the descriptor field of the associated map location and responds to the message based on the states of the flags.

Abstract: An information processing system according to the present invention judges whether or not an interruption accepted at a local processor for input/output control is to be terminated with the processing at the local processor only and if, the interruption is not to be terminated with such processing at the local processor only, notifies the main processor CPU of an interruption. Upon receipt of such interruption notice, the main processor CPU accesses the data area to store the input/output control information in local processor to prepare input/output control information. Then, the CPU of the main processor requests the input/output control section of the local processor to perform processing.

Abstract: A computer input system implementing a chord keyboard, with particular structuring of the encoding scheme for the chord keyboard, and a method of visual feedback of the operation of the keyboard presented in that structured form. The available characters are divided into groups, and a stroke of a chord either selects an active row or selects a character from the active row. A display provides the status of the keyboard system, including what actions the user has taken, and indicates what characters will be input depending on the user's subsequent actions. When a chord is pressed, this display shows the character that will be input if this chord were to be released, and the user has the opportunity to change the chord selected without inputting an undesired character. One characteristic of the particular structure is the separation of sets of 10 characters into subgroups of 4, 3, 2, and 1 characters, these subgroups being accessed with chords of 1, 2, 3, and 4 fingers respectively.

Abstract: The arbitrating method is based on the classification of the users into different categories, and the assignment to all users in a category of an identical privilege level which characterizes the interruption capability of the users in the category. A task performed by a selected user in a category can only be interrupted for granting access to the resource to a user in a category having a higher privilege level. Also a normal preference level is assigned to each user within a category, which determines the selection order of the users in the category. The privilege level of a user category combined with the preference level of each user constitutes the priority level of the user. The access to the resource is granted to a selected user having the highest priority level.

Abstract: A Peripheral Component Interconnect (PCI) bus for component level interconnection of processors, peripherals and memories. The PCI bus is a physical interconnect apparatus intended for use between highly integrated peripheral controller components and processor/memory systems. The PCI bus is intended as a standard interface at the component level in much the same way that ISA, EISA, or Micro Channel.TM. buses are standard interfaces at the board level. Just as ISA, EISA, and Micro Channel.TM. buses provide a common I/O board interface across different platforms and different processor generations, the PCI bus is intended to be a common I/O component interface across different platforms and different processor generations. The PCI bus lends itself to use as a main memory bus, and can be used with various cache memory techniques.

Abstract: A system for generating globally unique identifiers for objects in a distributed object oriented database. In one embodiment the system comprises at least two processors connected by means of a network to a processor executing a server process which provides globally unique identifiers for objects throughout the network. Each processor on the network may execute one or more client processes, each of which may run transactions against the database. Each such client process transmits a request to the server process which provides the globally unique identifiers when that client process requires a globally unique object identifier for objects which the requesting client process is creating. In response to the request, the server which provides globally unique identifiers transmits a range of globally unique object identifiers to the requesting client process. The requesting client process then allocates object identifiers from this range of globally unique object identifiers to the objects it is creating.

Abstract: An object of the present invention is to specify two disk drive apparatuses which are connected to an AT interface as a master or slave HDD for local or cable selection by only one jumper block. A disk drive apparatus connected to data processing means through a plurality of interface lines including one interface line connected to a first voltage level of said data processing means, including:a plurality of connection points connected respectively to said plurality of interface lines,a first connection point capable of being selectively connected to said one interface line,a second connection point kept at a floating voltage,a third connection point tied to the first voltage level,a fourth connection point tied to a second voltage level and selectively connected to one of said first, second, and third connection points, andcontrol means connected to said fourth connection point and recognizes itself as a first or second disk drive apparatus by detecting a voltage level of the fourth connection point.

Abstract: A data processing and transmission network includes plural information processing systems and shared sub-systems remote from the information processing systems. Each shared sub-system includes an I/O bus and a plurality of I/O bus interface logic circuits coupled to the bus. Each interface logic circuit is coupled to one of the system processing devices via a bidirectional fiber optic link, and thereby couples its associated processing device to the I/O bus. Further fiber optic links couple each system processing device to the I/O bus of each remaining sub-system through an associated I/O bus interface logic circuit. Each sub-system further includes multiple I/O devices, each device coupled to a device controller which in turn is coupled to the I/O bus.

Abstract: A communication control apparatus comprises a transmission control section for successively reading out words forming the transmission frame every once from a transmitting RAM in the case of transmission, a receiving control unit for writing the words forming the receiving frame every once in the case of receipt to a receiving RAM, an automatic transmitting timing setting section for repeating the above-described operation correspondingly to the number of frames every unit time in the case of transmission and receipt, and a plurality of transmission and receipt address base registers and transmission and receipt data base registers for storing therein a top address and a word length of the transmitting RAM and the receiving RAM every each transmitting and receiving frame.

Abstract: A method and apparatus for very low, in some case even zero, data latency accesses to a shared resource for devices such as disk drives and their channel formatting agents. The method and apparatus together will controllably terminate any non-low-latency access in process and then start a low latency access. Since the computer system has a group of three agents that may require low latency accesses, a special low latency arbitration method and apparatus is provided instead of the normal dynamic time loop arbitration. The low latency arbitration is call zero latency loop arbitration. The method and apparatus can actually provide zero latency data accesses for disk reads and writes in many cases. Once all low latency accesses are fulfilled, the method and apparatus allow the computer system to return to its slower, normal dynamic timed loop arbitration.

Abstract: A system and process are disclosed for configuring an Event Driven Interface and analyzing its output for monitoring and controlling a data communications network. The invention is a combination of a source of control vectors, which sends control vectors to a Programmable Performance Vector Generator which is coupled to a data communications network to be monitored and controlled. The control vectors configure an Event Driven Interface contained in the Programmable Performance Vector Generator, based upon the protocol of the network, performance information required, and the type of analysis and network characteristics required from the system. Event vectors are then output to an expert system which analyzes them and provides monitoring information and control signals to the network. The invention enables real-time load distribution, load balancing, problem determination, routing and customer services.

Abstract: A high-speed cache is shared by a plurality of independently-operating data systems in a multi-system data sharing complex. Each data system has access both to the high-speed cache and the lower-speed, secondary storage for obtaining and storing data. Management logic and the high-speed cache assures that a block of data obtained form the cache for entry into the secondary storage will be consistent with the version of the block of data in the shared cache with non-blocking serialization allowing access to a changed version in the cache while castout is being performed. Castout classes are provided to facilitate efficient movement from the shared cache to DASD.

Abstract: A compiler framework uses a generic "shell" and a generic back end (where the code generator is target-specific). The generic back end provides the functions of optimization, register and memory allocation, and code generation. The code generation function of the back end may be targeted for any of a number of computer architectures. A front end is tailored for each different source language, such as Cobol, Fortran, Pascal, C, C++, etc. The front end scans and parses the source code modules, and generates from them an intermediate language representation of the source code programs expressed in the source code. The intermediate language represents any of the source code languages in a universal manner, so the interface between the front end and back end is of a standard format, and need not be rewritten for each language-specific front end. A feature is a mechanism for representing effects and dependencies in the interface between front end and back end.