Abstract: To effect a block data transfer between a plurality of physical I/O devices coupled through interfaces to an I/O channel ("IOC") bus, a source logical device is established by programmably assigning to each of the physical device interfaces a logical device identifier, a leaf identifier determining when the physical device participates relative to the first data transfer in the block data transfer, a burst count specifying the number of consecutive transfers for which the physical device is responsible when its interleave period arrives, and an interleave factor identifying how often the physical device participates in the block data transfer. A destination logical device is similarly established. The source and logical devices are then activated to accomplish a block transfer of data between them.

Abstract: A software asynchronous communication protocol between two computers allows the roles of master and slave to be switched between the computers, depending on the nature and direction of the communication. In order to avoid truncating bit strings transmitted between the computers due to a difference in the write/read cycles of the computers, the software incorporates a dwell to accommodate the slowest computer in the system.

Abstract: Apparatus and method for programmably providing information on a dedicated output pin of an integrated circuit, which information is diagnostic about a plurality of nodes inside of said integrated circuit by connecting said plurality of nodes and a programmable set of binary gate signals to a combinatorial logic circuit and controlling the selection of said nodes being input to said logic circuit so that said combinatorial logic circuit provides a real time diagnostic signal to said dedicated output pin.

Abstract: A method for managing a data transfer between a first device and an allocated portion of common memory including the steps of receiving a reallocation request of the allocated portion of common memory from a second device, receiving a veto of the requested reallocation from the first device, and delaying the reallocation request. In addition, a method for transferring data between a peripheral device and a common memory in a virtual memory system including the steps of instructing the peripheral device to transfer data with an allocated portion of the common memory, requesting a reallocation of the allocated portion of the common memory, and receiving a veto of the requested reallocation from the peripheral device in response to the instructed data transfer.

Abstract: A bus interface system for expanding the I/O capability of a portable computer utilizes a parallel port connector with master interface circuitry connected to the internal ISA I/O bus of the portable computer and driving a 25-conductor Centronics-type cable as an intermediate bus. The master interface circuitry is device-driver-transparent, and multiplexes address, data, and control information over a byte-wide avenue of the intermediate bus according to premapped state translation tables. In a preferred embodiment a single peripheral I/O device comprising a slave circuitry may be connected to the 25-pin port, and the slave circuitry demultiplexes the intermediate bus states, providing a synthesized sub-set of ISA states to drive the peripheral device. In another embodiment a docking box comprises a bus with multiple I/O ports, such as a network port, a COM serial port, and additional floppy and hard disk drives.

Abstract: An apparatus for intersystem I/O channel paging. The I/O channel through an I/O channel adapter provides communication between a central processor, an I/O processor, and a shared electronic storage device. The central processor and I/O processor are each enabled for recognizing specific instructions. The intersystem channel may be implemented in the form of a page chain table. Either process is capable of constructing a page chain table in the shared electronic storage device, upon receipt of appropriate instructions. The central processor or I/O processor signals the I/O channel adapter with identification of a page chain table to select. The I/O channel adapter fetches table entries and executes the table. The I/O channel adapter initiates I/O activity upon execution of the table. The I/O channel is not dependent upon the central processor or I/O processor for fetching or executing instructions, rather it acts independent of the processors once the page chain table is created.