Abstract: The configuration of a cache is adjusted within a computer system that includes at least one entity that submits a stream of references, each reference corresponding to a location identifier corresponding to data storage locations in a storage system. The reference stream is spatially sampled using reference hashing. Cache utility values are determined for each of a plurality of caching simulations and an optimal configuration is selected based on the results of the simulations.

Abstract: A secondary storage controller receives metadata that uniquely identifies a source volume of a primary storage controller. Data stored in the source volume of the primary storage controller is synchronously copied to a target volume of the secondary storage controller. The secondary storage controller receives a command from a primary host to write selected data to the source volume. In response to receiving the command at the secondary storage controller, the selected data is written to the target volume of the secondary storage controller.

Abstract: An object-based storage system comprising a host system capable of executing applications for and with an object-based storage device (OSD). Exemplary configurations include a call interface, a physical layer interface, an object-based storage solid-state device (OSD-SSD), and are further characterized by the presence of a storage processor capable of processing object-based storage device algorithms interleaved with processing of physical storage device management. Embodiments include a storage controller capable of executing recognition, classification and tagging of application files, especially including image, music, and other media. Also disclosed are methods for initializing and configuring an OSD-SSD device.

Abstract: Various systems and methods are described for configuring a data storage system. In one embodiment, a plurality of actual capacities of a plurality of storage devices of the data storage system are identified and divided into a plurality of capacity slices. The plurality of capacity slices are combined into a plurality of chunks of capacity slices, each having a combination of characteristics of the underlying physical storage devices. The chunks of capacity slices are then mapped to a plurality of logical storage devices. A group of the plurality of logical storage devices is then organized into a redundant array of logical storage devices.

Abstract: The present disclosure relates to an interface comprising a memory controller and a memory unit coupled to the memory controller and configured to communicate with the memory controller through a first signal and a second signal. The interface further comprises a determination unit comprising judgment logic configured to send a control signal configured to align the first signal with the second signal. The memory controller further comprises a digitally-controlled delay line (DCDL) coupled to the determination unit and configured to receive the control signal, wherein the determination unit instructs the DCDL to adjust a delay of the first signal to align the first signal with the second signal. The memory controller further comprises a value register configured to store a signal delay value corresponding to alignment between the first signal with the second signal which is contained within the control signal. Other devices and methods are disclosed.

Abstract: A method including creating a transaction object for a transaction identified by a TOI and associated with an object identified by an OID, storing a TE and a MD frag for the transaction object, receiving a write request to write data to the transaction object, storing second TE including a TOI and offset and a data frag including the data, storing an entry including a hash value and a physical address of the data frag, and receiving a commit request to commit the transaction. In response to the commit request storing a third TE and a second MD frag for the transaction object, where the second MD frag identifies the object and specifies that the transaction is committed and updating a second entry including a second hash value and a second physical address for a second data frag to replace the second physical address with the physical address.

Abstract: Raw or unencrypted data is encrypted using a standard encryption algorithm and stored in a Flash memory array. The raw or unencrypted data may be pre-processed before it is encrypted. Pre-processing may include data scrambling, pre-encryption data mixing, or both. Data scrambling may involve an invertible transformation. The scrambled data may then be used to seed a sequence generator. Each output from the sequence generator may be processed using a bit-by-bit Exclusive Or (XOR) operation to impart random or pseudorandom statistical properties. Pre-encryption data mixing may combine the scrambled (or unscrambled) data with information that is unique to each chunk of data, as well as with a user-supplied secret key. This helps ensure that identical raw data chunks are not stored as identical encrypted data chunks in the Flash memory array.

Abstract: A memory controller, system including the memory controller and method of controlling the memory. The memory controller receives requests for memory and content sensitively allocates memory space in a mixed cell memory. The memory controller allocates sufficient space including performance memory storing a single bit per cell and dense memory storing more than one bit per cell. Some or all of the memory may be selectable by the memory controller as either Single Level per Cell (SLC) or Multiple Level per Cell (MLC).

Abstract: Various systems and methods for adjusting threshold access frequency based on cache pressure are disclosed. The threshold access frequency is adjusted based on a block of data in a storage volume that has an access frequency matching or exceeding the threshold access frequency. The threshold access frequency is used to determine whether the block of data should be inserted into the cache from the storage volume.

Abstract: Mechanisms are provided, in a storage system controller of a storage system, for writing data to a storage medium. The storage system controller receives a write request to write a block of data to the storage medium. The write request does not specify a location on the storage medium to which to write the block of data. The storage system controller determines a current position of a write mechanism of the storage system relative to the storage medium and determines a location on the storage medium to write the block of data based on the current position of the write mechanism. The storage system controller sends a notification to a host system identifying the location of the block of data on the storage medium as determined by the storage system controller. The writing mechanism writes the block of data to the determined location on the storage medium.

Abstract: The present invention relates to the field of digital media recording such as video or audio, where compression is used to reduce the amount of data to save onto a data storage. In particular the invention relates to recording media, wherein the memory area required to store the media is unknown. The invention discloses a method for recording digital streamed media with a number of media frames in a memory by encoding each media frame into an encoded frame comprising a first number of sets of data, representing different characteristics of the media stream. The invention further relates to detecting if the data storage is full and if the data storage is full, storing new frames in the data storage previously occupied by the data sets representing the least prioritized characteristics of the previously stored encoded frames. The invention also relates to a corresponding media recorder and computer program.

Abstract: A method, system, and computer program product for system-wide power conservation using memory cache are provided. A memory access request is received at a location in a memory architecture where processing the memory access request has to use a last level of cache before reaching a memory device holding a requested data. Using a memory controller, the memory access request is caused to wait, omitting adding the memory access request to a queue of existing memory access requests accepted for processing using the last level of cache. All the existing memory access requests in the queue are processed using the last level of cache. The last level of cache is purged to the memory device. The memory access request is processed using an alternative path to the memory device that avoids the last level of cache. A cache device used as the last level of cache is powered down.

Abstract: A method for memory migration between addressing schemes, including: receiving a first request to access a first memory address and a second request to access a second memory address; comparing the first memory address and the second memory address with a barrier pointer referencing a barrier address and separating migrated addresses and un-migrated addresses; tagging the first request with a first tag indicative of the first addressing scheme in response to the first memory address being on an un-migrated side of the barrier address; tagging the second request with a second tag indicative of the second addressing scheme in response to the second memory address being on a migrated side of the barrier address; and sending the first request to a first memory controller unit (MCU) and the second request to a second MCU.

Abstract: The described embodiments include a main memory and a cache memory (or “cache”) with a cache controller that includes a mode-setting mechanism. In some embodiments, the mode-setting mechanism is configured to dynamically determine an access pattern for the main memory. Based on the determined access pattern, the mode-setting mechanism configures at least one region of the main memory in a write-back mode and configures other regions of the main memory in a write-through mode. In these embodiments, when performing a write operation in the cache memory, the cache controller determines whether a region in the main memory where the cache block is from is configured in the write-back mode or the write-through mode and then performs a corresponding write operation in the cache memory.

Abstract: Storage tracks from at least one host are destaged from the write cache rank when it is determined that the at least one host is idle with respect to a first set of ranks, and storage tracks are refrained from being destaged from each rank when it is determined that the at least one host is not idle with respect to a second set of ranks.

Abstract: An information processing device includes a memory; and a processor that executes a program stored in the memory, wherein the processor executes an operation including: receiving first stream data and second stream data that each include a piece of reception data representing a set of a key and a numerical value, when detecting, from the second stream data, a piece of reception data with the same key as a key of a piece of reception data of the first stream data, obtaining a processing result by adding together numerical values of the pieces of reception data that have the same key, and storing the processing result in the memory.

Abstract: An asset management method implemented on an integrated circuit uses a keys memory storing keys, each key being associated with an asset identifier, and a data memory storing asset information. The method comprises: receiving an input command for an asset comprising an asset identifier and asset information, computing addresses to Keys memory from the asset identifier, the computing addresses comprising calculating hashes from the asset identifier, finding or allocating an entry in keys memory for the asset, based on the computed set of addresses, depending on the input command, computing a data address to the data memory for the asset from the address and position in the keys memory at which an entry has been found or allocated for the asset; reading data in the data memory at the computed data address; and executing the input command based on the data read in the data memory at the data address.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable local hash value generation in a non-volatile data storage system (e.g., using a flash memory device). In one aspect, rather than having Bloom filter logic in a host, Bloom filter functionality is integrated in the non-volatile data storage system. In some implementations, at a non-volatile data storage system, the method includes receiving from a host a plurality of requests that specify respective elements. The method further includes, for each respective element specified by the received requests, (1) generating a respective set of k bit positions in a Bloom filter, using k distinct hash functions, where k is an integer greater than 2, and (2) setting the respective set of k bit positions in the Bloom filter, which is stored in a non-volatile storage medium of the non-volatile data storage system.

Abstract: This invention hides the page miss translation latency for program fetches. In this invention whenever an access is requested by CPU, the L1I cache controller does a-priori lookup of whether the virtual address plus the fetch packet count of expected program fetches crosses a page boundary. If the access crosses a page boundary, the L1I cache controller will request a second page translation along with the first page. This pipelines requests to the ?TLB without waiting for L1I cache controller to begin processing the second page requests. This becomes a deterministic prefetch of the second page translation request. The translation information for the second page is stored locally in L1I cache controller and used when the access crosses the page boundary.

Abstract: This invention provides a current page translation register storing virtual to physical address translation data for a single current page and optionally access permission data for the same page for program accesses. If an accessed address is within the current page, the address translation and permission data is accessed from current page translation register. This current page translation register provides an additional level of caching of this data above the typical translation look-aside buffer and micro translation look-aside buffer. The smaller size of the current page translation register provides faster page hit/miss determination and faster data access using less power than the typical architecture. This is helpful for program access which generally hits the current page more frequently than data access.