Patents Examined by Matthew Bradley
  • System and method of hinted cache data removal
    Patent number: 9378151
    Abstract: The disclosure is directed to a system and method of cache management for a data storage system. According to various embodiments, the cache management system includes a hinting driver, a priority controller, and a data scrubber. The hinting driver generates pointers based upon data packets intercepted from data transfer requests being processed by a host controller of the data storage system. The priority controller determines whether the data transfer request includes a request to discard a portion of data based upon the pointers generated by the hinting driver. If the priority controller determines that data transfer request includes a request to discard a portion of data, the data scrubber locates and removes the portion of data from the cache memory so that the cache memory is freed from invalid data (e.g. data associated with a deleted file).
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: June 28, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Vineet Agarwal, Durga Prasad Bhattarai, Sourav Saha
  • Hash-based spatial sampling for efficient cache utility curve estimation and cache allocation
    Patent number: 9336141
    Abstract: Cache utility curves are determined for different software entities depending on how frequently their storage access requests lead to cache hits or cache misses. Although possible, not all access requests need be tested, but rather only a subset, determined by whether a hash value of each current storage location identifier (such as an address or block number) meets one or more sampling criteria.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 10, 2016
    Assignee: CLOUD PHYSICS, INC.
    Inventors: Carl A Waldspurger, Nohhyun Park
  • Shared function multi-ported ROM apparatus and method
    Patent number: 9336008
    Abstract: Various embodiments may be disclosed that may share a ROM pull down logic circuit among multiple ports of a processing core. The processing core may include an execution unit (EU) having an array of read only memory (ROM) pull down logic storing math functions. The ROM pull down logic circuit may implement single instruction, multiple data (SIMD) operations. The ROM pull down logic circuit may be operatively coupled with each of the multiple ports in a multi-port function sharing arrangement. Sharing the ROM pull down logic circuit reduces the need to duplicate logic and may result in a savings of chip area as well as a savings of power.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: May 10, 2016
    Assignee: INTEL CORPORATION
    Inventors: Satish K. Damaraju, Subramaniam Maiyuran
  • Multi-core interconnect in a network processor
    Patent number: 9330002
    Abstract: A network processor includes multiple processor cores for processing packet data. In order to provide the processor cores with access to a memory subsystem, an interconnect circuit directs communications between the processor cores and the L2 Cache and other memory devices. The processor cores are divided into several groups, each group sharing an individual bus, and the L2 Cache is divided into a number of banks, each bank having access to a separate bus. The interconnect circuit processes requests to store and retrieve data from the processor cores across multiple buses, and processes responses to return data from the cache banks. As a result, the network processor provides high-bandwidth memory access for multiple processor cores.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: May 3, 2016
    Assignee: Cavium, Inc.
    Inventors: Richard E. Kessler, David H. Asher, John M. Perveiler, Bradley D. Dobbie
  • False power failure alert impact mitigation
    Patent number: 9329954
    Abstract: Various embodiments of the present invention that include receive a signal indicating a loss of power, start a timer, the timer configured to expire after a specific time period, copy write cache data from the volatile memory to a solid state device (SSD), upon receiving the signal indicating the loss of power to the storage system, configure the SSD as both a read cache and the write cache, perform a health test on the storage system, determine the loss of power as a false alarm if the timer expires and the storage system passes a health test on the storage system upon receiving the signal indicating the loss of power, and upon the timer expiring and the storage system passing the health test, copy the write cache data from the SSD back to the volatile memory.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: May 3, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence C. Blount, Itzhack Goldberg, Neil Sondhi
  • Systems and methods for background destaging storage tracks
    Patent number: 9323694
    Abstract: Storage tracks from at least one server are destaged from the write cache rank when it is determined that the at least one server is idle with respect to a first set of ranks, and storage tracks are refrained from being destaged from each rank when it is determined that the at least one server is not idle with respect to a second set of ranks such that storage tracks in the first set of ranks may be destaged while storage tracks in the second set of ranks are not being destaged.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: April 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent C. Beardsley, Michael T. Benhase, Binny S. Gill, Lokesh M. Gupta, Sonny E. Williams
  • Zero-copy caching
    Patent number: 9323693
    Abstract: Caching of an immutable buffer that has its data and address prevented from changing during the lifetime of the immutable buffer. A first computing entity maintains a cache of the immutable buffer and has a strong reference to the immutable buffer. So long as any entity has a strong reference to the immutable buffer, the immutable buffer is guaranteed to continue to exist for the duration of the strong reference. A second computing entity communicates with the first computing entity to obtain a strong reference to the immutable buffer and thereafter read data from the immutable buffer. Upon reading the data from the cache, the second computing entity demotes the strong reference to a weak reference to the immutable buffer. A weak reference to the immutable buffer does not guarantee that the immutable buffer will continue to exist for the duration of the weak reference.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: April 26, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jinsong Yu, Andrew E. Goodsell, F. Soner Terek, Christopher Wellington Brumme, Ahmed Hassan Mohamed
  • System and method for thin provisioning
    Patent number: 9317419
    Abstract: A method, computer program product, and computing system for grouping storage blocks within a file system into a plurality of storage pools including a free-backed storage pool, a free-unbacked storage pool, and an allocated-backed storage pool. The free-backed storage pool identifies unused storage blocks within the file system that are already associated with physical storage space within a backend storage system. The free-unbacked storage pool identifies unused storage blocks within the file system that are not yet associated with physical storage space within the backend storage system. The allocated-backed storage pool identifies used storage blocks within the file system that are already associated with physical storage space within the backend storage system. A request is received for one or more unused storage blocks within the file system.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 19, 2016
    Assignee: EMC Corporation
    Inventors: Jean-Pierre Bono, Morgan A. Clark, Michael D. Scheer, William C. Davenport, Sairam Veeraswamy
  • Indexed page address translation to reduce memory footprint in virtualized environments
    Patent number: 9317441
    Abstract: Embodiments of systems, apparatuses, and methods for performing guest logical memory address to host physical memory address translation are described. In some embodiments, a system receives the guest logical memory address and determines an index page reference from the guest logical memory address. The system further retrieves a page index corresponding to the virtual machine. In addition, the system retrieves a first part of the host physical memory address from index page using the page index and a second part of the host physical memory address from the guest logical memory address. The system generates the host physical memory address from the first and second parts of the host physical memory address.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: April 19, 2016
    Assignee: Intel Cororation
    Inventor: Sebastian Schoenberg
  • Systems and methods for background destaging storage tracks
    Patent number: 9317447
    Abstract: Storage tracks from at least one host are destaged from the write cache rank when it is determined that the at least one host is idle with respect to a first set of ranks, and storage tracks are refrained from being destaged from each rank when it is determined that the at least one host is not idle with respect to a second set of ranks such that storage tracks in the first set of ranks may be destaged while storage tracks in the second set of ranks are not being destaged.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: April 19, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent C. Beardsley, Michael T. Benhase, Binny S. Gill, Lokesh M. Gupta, Sonny E. Williams
  • Storage system and methods of mapping addresses of snapshot families
    Patent number: 9311014
    Abstract: There is provided a storage system capable to maintain a snapshot family comprising a plurality of members having hierarchical relations therebetween, and a method of operating thereof.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: April 12, 2016
    Assignee: INFINIDAT LTD.
    Inventors: Josef Ezra, Yechiel Yochai, Ido Ben-Tsion, Efraim Zeidner
  • Memory with mixed cell array and system including the memory
    Patent number: 9311009
    Abstract: A memory system, system including the memory system and method of reducing memory system power consumption. The memory system includes multiple memory units allocable to one of a number of processor units, e.g., processors or processor cores. A memory controller receives requests for memory from the processor units and allocates sufficient space from the memory to each requesting processor unit. Allocated memory can include some Single Level per Cell (SLC) memory units storing a single bit per cell and other memory units storing more than one bit per cell. Thus, two processor units may be assigned identical memory space, while half, or fewer, than the number of cells of one are assigned to the other.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: April 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: Bing Dai, Chung H. Lam, Jing Li
  • Storage array system and non-transitory recording medium storing control program
    Patent number: 9304685
    Abstract: According to the embodiments, a storage array system includes a plurality of storage units, and a host device. The host device determines whether first data, which is restored from data in the storage units other than a replaced first storage unit, is identical with data indicated by a first function. The host device transmits and writes the first data to the first storage unit, when the first data is not identical with the data indicated by the first function. The host device transmits a deletion notification to the first storage unit, when the first data is identical with the data indicated by the first function.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: April 5, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Hashimoto, Koichi Nagai
  • Affinity group access to global data
    Patent number: 9304921
    Abstract: A method, system, and computer readable medium to share data on a global basis within a symmetric multiprocessor (SMP) computer system are disclosed. The method may include grouping a plurality of processor cores into a plurality of affinity groups. Global data may be copied into a plurality of group data structures. Each group data structure may correspond to an affinity group. The method may read a first group data structure by a thread executing on a processor core associated with a first affinity group.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Stuart Z. Jacobs, David A. Larson
  • Verification of dynamic logical partitioning
    Patent number: 9298516
    Abstract: Embodiments of the present invention disclose a method, computer program product, and system for verifying transitions between logical partition configurations. A computer system divides the physical resources of a processing core into logical partitions, each of which has at least one processing subcore. The computer system loads the contexts of the logical partitions and assigns test cases to each processing subcore. The processing subcore executes the test case, verifying the context of the logical partition. The computer system reassigns the test cases to different processing cores in anticipation of reconfiguring the number of logical partitions on the processing core. The computing system reconfigures the number of logical partitions on the processing core and executes the test cases as assigned on the reconfigured logical partitions.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: March 29, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Manoj Dusanapudi, Varun Mallikarjunan
  • Writing adjacent tracks to a stride, based on a comparison of a destaging of tracks to a defragmentation of the stride
    Patent number: 9298645
    Abstract: Compressed data is maintained in a plurality of strides of a redundant array of independent disks, wherein a stride is configurable to store a plurality of tracks. A request is received to write one or more tracks. The one or more tracks are written to a selected stride of the plurality of strides, based on comparing the number of operations required to destage selected tracks from the selected stride to the number of operations required to defragment the compressed data in the selected stride.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: March 29, 2016
    Assignee: International Business Machines Corporation
    Inventor: Lokesh M. Gupta
  • Memory with mixed cell array and system including the memory
    Patent number: 9298383
    Abstract: A memory system, system including the memory system and method of reducing memory system power consumption. The memory system includes multiple memory units allocable to one of a number of processor units, e.g., processors or processor cores. A memory controller receives requests for memory from the processor units and allocates sufficient space from the memory to each requesting processor unit. Allocated memory can include some Single Level per Cell (SLC) memory units storing a single bit per cell and other memory units storing more than one bit per cell. Thus, two processor units may be assigned identical memory space, while half, or fewer, than the number of cells of one are assigned to the other.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: March 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Bing Dai, Chung H. Lam, Jing Li
  • Affinity group access to global data
    Patent number: 9298622
    Abstract: A method, system, and computer readable medium to share data on a global basis within a symmetric multiprocessor (SMP) computer system are disclosed. The method may include grouping a plurality of processor cores into a plurality of affinity groups. Global data may be copied into a plurality of group data structures. Each group data structure may correspond to an affinity group. The method may read a first group data structure by a thread executing on a processor core associated with a first affinity group.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: March 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Stuart Z. Jacobs, David A. Larson
  • Control logic design to support USB cache offload
    Patent number: 9286203
    Abstract: A redundant array of independent drives controller and board controlled cache off-loading during a power failure is described. Methods associated with the use of the redundant array of independent drives controller and board for controlled cache off-loading during a power failure are also described.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: March 15, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Moby J. Abraham, Lakshmana M. Anupindi, R. Brian B. Skinner, James A. Rizzo, Mark J. Jander
  • Verification of dynamic logical partitioning
    Patent number: 9286133
    Abstract: Embodiments of the present invention disclose a method, computer program product, and system for verifying transitions between logical partition configurations. A computer system divides the physical resources of a processing core into logical partitions, each of which has at least one processing subcore. The computer system loads the contexts of the logical partitions and assigns test cases to each processing subcore. The processing subcore executes the test case, verifying the context of the logical partition. The computer system reassigns the test cases to different processing cores in anticipation of reconfiguring the number of logical partitions on the processing core. The computing system reconfigures the number of logical partitions on the processing core and executes the test cases as assigned on the reconfigured logical partitions.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: March 15, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Manoj Dusanapudi, Varun Mallikarjunan