Abstract: A system and method for merging a plurality of sorted lists using multiple processors having access to a common memory in which N sorted lists which may exceed the capacity of the common memory are merged in a parallel environment. Sorted lists from a storage device are loaded into common memory and are divided into a number of tasks equal to the number of available processors. The records assigned to each task are separately sorted, and used to form a single sorted list. A multi-processing environment takes advantage of its organization during the creation of the tasks, as well as during the actual sorting of the tasks.

Abstract: A method of using a computer to execute a computer program, in which a caller portion of the program calls a callee function that returns a data structure. Before the callee function is called, the computer is used to determine whether the structure is to be used, and if so, an address to which the structure is to be returned is determined. The caller passes this address to the called function. The callee executes, and if the structure is to be used, the callee copies the structure to the predetermined address.

Abstract: A distributed processing system distributively performs a series of processes for a job at a plurality of processing units connected to a common transmission path and has a circuit for transmitting information from a processing unit to the common transmission path. The distributed processing system includes a circuit for receiving from the common transmission path the information required for the processing of a program stored in each processing unit, and a circuit for detecting if all the information required for the processing of the program has been collected, for performing the processing of the program using the collected information as input information for the processing and for transmitting the processed result data to the common transmission path.

Abstract: An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead. The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communication station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times.

Abstract: Apparatus for providing data available interrupts that have a variable threshold for reading data from a receiver FIFO, and for selecting the depth of a variable depth FIFO for use as either the receiver or transmitter FIFO of a UART. The interrupt circuit determines if the FIFO data level is at or exceeds a preselected threshold value, and if it doesn't, triggers the reduction of the threshold level after a preselected period of time if there has been no access of the FIFO. If the data available level is still less than the reduced threshold value, the threshold value is again reduced by a preselected value following each elapse of a second preselected pause between each resetting of the threshold level until either a data available interrupt occurs, the threshold level is dropped to zero, or the FIFO is accessed. Whenever the receiver FIFO is accessed, the threshold level is reset to the original preselected level.

Abstract: For use with a multiprocessor system employing shared memory, a software controlled method maintains cache coherency and execution synchronization among processors. A processor executing a SEND instruction transfers a cache line to one or more processors executing a RECEIVE instruction in a synchronized manner. The processors also execute the SEND and RECEIVE instructions to synchronize the execution of iterations of a program loop whereby a control processor distributes indices of the iterations to be performed by each worker processor.

Abstract: A computer system having a multi-module memory system. Accesses to the memory modules for reading or writing are undertaken in parallel. The memory system is addressed by input addresses. The memory system includes a map unit for transforming the input addresses to output addresses in a pseudo-random manner so as to tend to distribute memory accesses uniformly among the memory modules whereby contention resulting from multiple concurrent attempts to access the same memory module is reduced. The map unit performs addresses transforms that are repeatable so that the same input address maps to the same output address and that are one-to-one such that each input address maps to one and only one output address.

Abstract: A device and method provide for an accurate output from a unit, such as an oscillator and/or clock providing an output indicative of frequency and/or time. The device includes a processing section having a microprocessor that develops a model characterizing the performance of the device, including establishing predicted accuracy variations, and the model is then used to correct the unit output. An external reference is used to provide a reference input for updating the model, including updating of predicted variations of the unit, by comparison of the reference input with the unit output. The ability of the model to accurately predict the performance of the unit improves as additional updates are carried out, and this allows the interval between the updates to be lengthened and/or the overall accuracy of the device to be improved. The accuracy of the output is thus adaptively optimized in the presence of systematic and random variations.

Abstract: In a data processing system, a processor issues a transfer request through a data transfer controller to an extended buffer memory to elicit an accept signal. If the accept signal is not returned from the buffer memory within a specified period, a first dummy signal is generated instead, and the controller notifies this fact to the processor and waits for the return of an advance notice from the buffer memory. If the advance notice is not returned within a specified period, a second dummy signal is generated instead to allow the controller to proceed to transfer data read out of the buffer memory to a main memory. The controller then waits for the return of a status report signal from the buffer memory. If the status report signal is not received within a specified period, a third dummy signal is generated instead to allow the controller to proceed to examine a status signal from the buffer memory to determine whether the transferred data has been correctly read out of the buffer memory.

Abstract: Apparatus and method for insuring data cache content integrity among parallel processors is provided. Each processor has a data cache to store intermediate calculations. The data cache of each processor is synchronized with each other through the use of synchronization intervals. During entry of a synchronization interval, modified data variables contained in an individual cache are written back to a shared memory. The unmodified data contained in a data cache is flushed from memory. During exiting of a synchronization interval, data variables which were not modified since entry into the synchronization interval are also flushed. By retaining modified data cache values in the individual processors which computed the modified values, unnecessary access to shared memory is avoided.

Abstract: A single instruction multiple datastream (SIMD) polymorphic mesh network array processing system is modified by the inclusion of a single instruction multiple address (SIMA) circuit including a content addressable packet buffer memory to enable processing of an algorithm representing an arbitrary graph. Packets of address information and related data information associated with each independently addressable processing element forming the polymorphic mesh network array are transferred between the processing elements in accordance with one of a first-available method, a force transfer method, or a buffer sensitive method.

Abstract: A network interface board provides a communication link between a personal computer and a network bus connecting a plurality of programmable logic controllers. The network interface board mounts in an expansion slot of the personal computer. The programmable logic controllers control the operation of various machines. The network interface board includes mailbox registers for storing messages from the network, including three different queues of alarm messages which the personal computer can access in any order. These messages could be in the form of program steps, allowing the personal computer to directly program a programmable logic controller over the communication network.

Abstract: A system for determining the physical location of nodes on a network. The system includes two stations each of which has a clock. Each station uses its clock to determine the arrival times at the station of a packet transmitted over the network from a first node to a second node and of a reply packet sent by the second node to the first node. The arrival times of the packets and the corresponding reply packets are then used to calculate the distance along the network which separates the first and second node. Measurement of packet arrival times for all of the nodes yields the position of all of the nodes on the network.

Abstract: In the P operation of a semaphore operation, the semaphore priority set in the semaphore is compared with the process priority of an execution process. When the semaphore priority is higher than the process priority of the execution process, the process priority is changed to the semaphore priority and the process is executed in accordance with the changed process priority. In the V operation, on the other hand, the semaphore priority is compared with the process priority of the first process which is placed in the wait state. When the semaphore priority is higher than the process priority of the first process in the wait state, the process priority is changed to the semaphore priority and the process is placed in the ready state. Furthermore, the process priority of the process in the ready state is compared with the process priority of an execution process.

Abstract: An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead. The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communication station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times.

Abstract: A multiprocessor system includes a plurality of identical central subsystem (CSS) units, a plurality of memory subsystem units and input/output units which connect in common to a system bus. Requests are transferred between a pair of units on a priority basis defined by a distributed bus priority network included as part of the system bus. Each CSS unit includes cycle stealer logic circuits which grant bus cycles on a round robin basis. The cycle stealer logic circuits are connected to receive high priority request signals from the network and refuse acceptance of a cycle granted to such CSS unit as a low priority requester thereby passing it along to a next lower priority CSS unit.

Abstract: A rename tracking and propagation facility propagates renames, executed in multiple isolated file system name spaces (FSNS), to a remote FSNS on a per object basis without corruption of the remote FSNS names. In propagating an object's rename, the smallest set of additional object's renames which must be applied in the remote FSNS in order to apply the object's rename in the remote FSNS is determined. The set of renames is applied in the correct order, in the remote FSNS, accounting for those renames already propagated to the remote FSNS. A record of renames executed in a FSNS is utilized to determine which renames are to propagated. To accommodate parallel development (multiple users modifying part of the fill system all the time without explicit locking), name collisions in the remote FSNS are detected and resolved. These sets of renames are constructed such that they can be applied to the remote FSNS in any order.

Abstract: A multiple disk drive array storage device emulates the operation of a single disk drive. The array storage device includes a large buffer memory and a plurality of asynchronously-operating disk drives. A full physical track of data from each of the disk drives within the array is stored within the buffer memory and concatenated to create a large logical track of data. The large buffer memory and asynchronously-operating disk drives results in a data transfer rate that is faster than the standard disk drive architecture.

Abstract: The method uses statistical information obtained by running the computer code with test data to determine a new ordering for the code blocks. The new order places code blocks that are often executed after one another close to one another in the computer's memory. The method first generates chains of basic blocks, and then merges the chains. Finally, basic blocks that were not executed by the test data that was used to generate the statistical information are moved to a distant location to allow the blocks that were used to be more closely grouped together.

Abstract: A method and apparatus for loading a data value for a future LOAD instruction in a microprocessor by predicting the LOAD instruction's effective address. At each occurrence of a LOAD instruction, the effective address used is stored in a memory array which stores a last effective address and a next-to-last effective address. At a specified period before each LOAD instruction, the microprocessor loads a data value from a predicted effective memory address computed from the memory array. The predicted effective memory address is equal to the last effective address plus the difference between the last effective address and the next-to-last effective address. If the predicted effective address equals the actual effective address of the future LOAD instruction, the loaded data value is used.