Abstract: A microprogram loaded in a microprogram memory by a host CPU is read out by a microprogram read control circuit in a vacant period existing in each cycle of operation of a hardware unit, whereby the microprogram is transmitted to each circuit of the hardware unit through a microprogram read-only bus. Each circuit of the hardware unit comprises a decoder and operation thereof is controlled based on a microinstruction decoded by the decoder.

Abstract: A microinstruction executing system includes a sequencer for controlling sequential readout of microinstructions from a ROM for storage in a microinstruction register and for subsequent decoding by a decoder. In response to a destination control signal (source side) from the decoder, a general register will transfer data to a destination bus and in response to a destination control signal (destination side) from the decoder, data from the destination bus will be transferred to one of a destination data register or a source data register. In response to a source control signal (source side) from the decoder, the general register will transfer data to a source bus and in response to a source control signal (destination side) from the decoder data from the source bus will be transferred to one of the destination data register or source data register.

Abstract: A controller has a node interface logic (40), a ring bus interface logic (42), a set of input pins (44) and a set of output pins (45). A common logic (58) is connected to the node interface logic (40) and to the ring bus interface logic (42). The common logic includes an output FIFO buffer (32) connected to an output link interface (37) and an input FIFO buffer (34) connected to an input link interface (36). A mode select pin (43) is provided for selecting a node controller mode of operation and a ring controller mode of operation. The node interface (40) responds to assertion of the selection pin (43) to activate the pins (44, 45) with respect to the node interface (40). The ring bus interface (42) responds to deassertion of the select pin (43) to activate the pins (44, 45) with respect to the ring bus interface (42).

Abstract: A method for reading data blocks from main memory by central processing units in a multiprocessor system containing write-back caches. Load or gather instructions contain a write-intent flag. The status of the write-intent flag is determined. It is also determined whether a data block requested in the instruction by one of the processors is located in a corresponding cache, and if so, the requested data block is returned to the processor. If the data block is not in the cache and the write-intent flag indicates that the block will not be modified, the data block is read from main memory without obtaining a write privilege. The requested data block is subsequently returned from the cache to the processor. If the data block is not in the cache and the write-intent flag indicates the data block will be modified by the processor, then the data block is read from main memory while obtaining the write privilege. Subsequently, the requested data block is returned from the cache to the processor.

Abstract: An array processor includes a master array controller and sequencer (12) and a plurality of slave processors (20a)-(20n). The master generates sequencing commands for sequencing instruction flow in each of the slave processors. The slave processors generate addresses for associated memories (34a)-(34n). The data outputs of the memories are interfaced through a cross point switch (22) to a slave data processor (24). The master (12) is operable to initialize all of the slave devices to a starting address for an internal routine and sequence the instruction flow therein in a synchronous and parallel manner to execute a particular task.

Abstract: An improved multiprocessor system of the type including a plurality of processors and an array of memories interconnected by an interrogation logic where the processors have a store-in cache is presented. In such processors the most recent copy of the data does not always reside in the memories but can reside in a processor's cache necessitating cross-interrogation producing system delays. These delays are reduced by a fetch buffer selectively coupled to each memory for holding data before cross-interrogation and other checks are complete.

Abstract: A data transfer system to transfer variable-length data from a channel unit to a peripheral storing medium in which a channel adapter and a storing medium control unit are disposed between a channel unit and a data storing medium. These components are linked by means of a signal transmission path. The channel unit transmits a data signal and a command signal including an instruction designating a storage of the data and information specifying a length of the data to the storing medium control unit. On receiving the command signal from the channel unit, the storing medium control unit supplies the information specifying the length of the data in the command signal to a count unit of the channel adapter. The information is then set to the count unit of the channel adapter.

Abstract: A look-ahead flag generator generates a flag signal corresponding to the occurrence of a predetermined value stored in a counter (10). The output of the counter outputs any of a plurality of values, the values including the predetermined value and at least one boundary value that is one unit of increment or decrement displaced from the predetermined value. A clock signal source (13) is coupled to a first input of the counter (10) to indicate a decrement or an increment to the value stored in the counter (10). An up/down signal source (11) is coupled to a second input of the counter to indicate whether an increment or a decrement of the stored value should be performed. Predetermined states of the up/down signal and the clock signal are operable to cause a boundary value stored in the counter (10) to be changed to the predetermined value. A predecoder (12) is coupled to an output of counter (10) for decoding the boundary value. A latch (132) stores the decoded boundary value.

Abstract: A program counter display device having a program memory which stores a source program. An interpreter reads out the source program from the program memory and executing it. A program list generator generates a program list of the program stored in the program memory, and a program flow monitor having knowledge of the program flow determines the program flow in accordance with the statement currently being executed. A control structure monitor correlates the current statement supplied from the interpreter with a program control structure, and checks the balance of the program control structure such as the existence of an end in a loop structure, the existence of a destination of a branch sentence, etc. A program counter-mark generator connected to the program flow monitor and the control structure monitor generates a program counter mark indicating the program counter function, the program flow, and the control sturcture.

Abstract: A microcomputer universal package has testing terminals and switching circuitry for selecting first and second operations. In the first operation, as an evaluator type, a test device is connected to the testing terminals of the package. In the second operation, as a piggyback type, a rewritable ROM (EPROM) is connected to the testing terminals of the package. The testing terminals are automatically switched for the particular operation by the switching circuitry. Accordingly, the same device can be used as the evaluator type chip and the piggyback-type chip, which reduces the time and the cost of developing the program. In addition, since the piggyback-type chip, the evaluator-type chip, and a mask-type ROM chip can be constructed with the same pin arrangement, the program can be evaluated by the evaluator-type chip in the mask-type ROM mounting board that becomes the final product without requiring an interface board.

Abstract: A multiprocessor system is comprised of a bus and a plurality of processor modules. Each processor module includes a bus arbitration block, a bus access control block, an address output block, a data input/output block, a clock signal generating block, a stop request block for requesting the stop of supplying a clock signal, an operation processing block for processing data, and a stop control block. The stop control block stores the contents of the bus access (a type of the bus, the address and data concerning the access, etc.) as is made by the operation processing block when the clock signal is stopped, and to what clock of that access cycle the bus access proceeds. The stop control block controls the bus arbitration block to electrically disconnect the processor module from the bus. After the restart of supplying the clock signal, the bus arbitration block, the bus access control block, the address output block and the data input/output block are restored on the basis of the contents of the bus access.

Abstract: In a computer system, the flow of data from the execution unit to the cache 28 is enhanced by pairing individual, sequential longword write operations into a simultaneous quadword write operation. Primary and secondary writebuffers 50, 52 sequentially receive the individual longwords during first and second clock cycles and simultaneously present the individual longwords over a quadword wide bus to the cache 28. During the first clock cycle, when the cache 28 is not performing the quadword write operation, the cache 28 is free to perform the requisite lookup routine on the address of the first longword of data to determine if the quadword of address space is available in the cache. Thus, the flow of data to the cache 28 is maximized.

Abstract: A system for controlling virtual main memories (VMMs) of a plurality of virtual machines (VMs) which has a section for detecting an overload state of a VMM of any VM, a section for requesting a VMM corresponding to a required capacity in response to the detection. The system also includes a section for monitoring load states of the VMMs of other VMs in response to this request, a section for selecting an unbusy VM in accordance with the monitoring, a section for releasing the VMM corresponding to the requested capacity from the selected VM, and a section for supplying the released VMM to the VM requesting a VMM.

Abstract: A data processor bus in which information is transferred between agents attached to the bus by issuing request packets that request data from an agent on the bus and reply packets that return data requested by a request packet. A control method mixes request-and-reply packets on the bus by determining the use of a next-bus cycle using arbitration, reply deferral, and specification lines and the state of a grant queue and a pipe queue in accordance with a specified protocol. A request is forced to take the next available bus cycle upon the condition that there is an agent identified in the great queue and the pipeline queue is not full. A reply packet is forced to take the next available bus cycle upon the condition that the pipeline queue is full. A reply packet is forced to take the next available bus cycle upon the condition that the grant queue is empty and the pipeline queue is not empty. Giving requests precedence over replies to allows the pipeline to be kept as full as possible.

Abstract: A vector processor which maintains synchronization with an associated CPU by limiting the operational instruction proceedings. The vector processor utilizes an instruction register to store instructions from the CPU logical operations circuitry word processing in parallel with the CPU in accordance with instructions from the instruction register and a counter which increases in response to a start instruction from the CPU and decreases in response to the completion of an operation by the logical operation circuitry. A restraining signal is generated in response to a prescribed count of the counter, which delays the execution of the microprogram by the CPU. An indicator device is used for indicating storage of an instruction in the instruction register and a flag device is set in response to a start instruction from the CPU which actuates the indicator means even if no instruction is stored in the instruction register.