Abstract: A method and system for handling interrupts within a computer system during hardware resource migration are disclosed. In at least some embodiments, the method includes (a) programming an address conversion component so that incoming interrupt signals are directed to a control component rather than to a source processing resource, and (b) accumulating the incoming interrupt signals at the control component. Additionally the method also includes, subsequent to the migration of the partition from the source processing resource to a destination processing resource, (c) sending the accumulated incoming interrupt signals to the destination processing resource, and (d) reprogramming the address conversion component so that further incoming interrupt signals are directed to the destination processing resource.

Abstract: Hardware interrupts are routed to one of multiple processors of a virtualized computer system based on priority values assigned to the codes being executed by the processors. Each processor dynamically updates a priority value associated with code being executed thereby, and when a hardware interrupt is generated, the hardware interrupt is routed to the processor that is executing a code with the lowest priority value to handle the hardware interrupt. As a result, routing of the interrupts can be biased away from processors that are executing high priority tasks or where context switch might be computationally expensive.

Abstract: An apparatus for transmitting data across a high-speed serial bus includes an IEEE 802.3-compliant PHY having a GMII interface; an IEEE 1394-compliant PHY in communication with the IEEE 802.3-compliant PHY via a switch; the switch determining whether data transmission is be routed to the IEEE 802.3-compliant PHY or the IEEE 1394-compliant PHY; a first connection, the first connection for transmitting data between a device and the IEEE 802.3-compliant PHY; and a second connection, the second connection for transmitting data between a device and the IEEE 1394-compliant PHY.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.

Abstract: Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry including: at least one input for receiving transaction requests from at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; and at least one path for transmitting transaction requests between at least one input and at least one output. Also includes is control circuitry for routing the received transaction requests from at least one input to at least one output and responds to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths. Barrier transaction requests include an indicator of transaction requests whose ordering is to be maintained.

Abstract: A connector assembly includes first and second connectors, a flexible printed circuit board, first and second peripheral component interconnection express (PCIe) slots, and a jumper card. When the jumper card is plugged into the first PCIe slot, pins of the jumper card are connected to pins of the first PCIe slot for transmitting signals to the pins of the first PCIe slot and to the pins of the first connector in that order. When the first connector is connected to the second connector, signals at the pins of the first PCIe slot are transmitted to pins of the second PCIe slot.

Abstract: A method for use in deploying computers into a data center includes calculating in a computer an expected peak power draw for a plurality of computers. The expected peak power draw for the plurality of computers is less than a sum of individual expected peak power draws for each computer from the plurality of computers.

Abstract: A method, apparatus, and program product manage scheduling of a plurality of jobs in a parallel computing system of the type that includes a plurality of computing nodes and is disposed in a data center. The plurality of jobs are scheduled for execution on a group of computing nodes from the plurality of computing nodes based on the physical locations of the plurality of computing nodes in the data center. The group of computing nodes is further selected so as to distribute at least one of a heat load and an energy load within the data center. The plurality of jobs may be additionally scheduled based upon an estimated processing requirement for each job of the plurality of jobs.

Abstract: Disclosed herein is a data transfer device to which a master device that issues transfer requests and slave devices each having a function of responding to the transfer request may be connected. The device may include a transfer request counter that counts up or down each time a response signal is inputted thereto from any slave device, and counts down or up each time a data transfer completion signal is inputted thereto; a transfer destination selector that, based on a count value of the counter and information concerning a transfer-target slave device, determines and selects one of the slave devices as a destination of the transfer request, and connects the master device with the selected slave device; and a data transfer monitoring section that monitors completion of data transfer corresponding to the transfer request and, upon recognizing the completion, outputs the data transfer completion signal to the counter.

Abstract: An information handling system includes at least two processing systems that share system resources. In response to detecting a designated event, a power control module of the information handling system can select one of a plurality of available power profiles. The power profile can be selected based on the event and state information indicative of a state of the processing systems. Based on the selected profile, the power control module can set an operational power mode of one or more of the shared system resources.

Abstract: Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.

Abstract: A USB electronic device with a power source loaded therein, which is connected to another USB electronic device via a USB connector, comprises a voltage detection unit that detects a voltage at an identification pin of the USB connector, a power supply control unit that controls connection/disconnection between a power supply pin of the USB connector and the power source based upon a change in voltage at the identification pin detected by the voltage detection unit and an allow/disallow control unit that executes control to allow/disallow detection of the voltage change at the identification pin.

Abstract: When a user presses down an extension directing button, a control unit of an image forming apparatus detects the press-down of the extension directing button and executes a setting process of new mode set time. In this case, the control unit calculates the new mode set time by adding extension time extracted from an extension time data storage unit to basic set time acquired from a basic set time data storage unit and records the new mode set time in a mode set time data storage unit. Then, when start of a sleep mode is detected, the control unit of the image forming apparatus records the basic set time, which is extracted from the basic set time data storage unit, in the mode set time data storage unit as new mode set time when the mode set time is extended.

Abstract: A docking station is provided for a computing device. The docking station may be used by, for example, a mobile computing device, such as a cellular or wireless telephony/messaging device. The docking station includes a housing comprising a receiving surface top receive and retain the mobile computing device. An inductive signal transfer interface is included with the housing to inductively signal at least one of power or data to the mobile computing device. The docking station further provides an output component and processing resources. The processing resources are configured to detect placement of the mobile computing device on the receiving surface. The data is received from the mobile computing device, and an output is signaled to the output component based on the received data.

Abstract: In order to provide a solution for performing priority arbitration, a mask and reset-mask are generated in concert with a priority arbitration scheme. A plurality of requestors may issue requests for a shared resource. The priority arbitration scheme may grant access to a single requestor for a single priority assignment period. The mask may assist the priority arbitration scheme to assign priority to the plurality of requestors by temporarily removing a subset of the plurality of requestors for a particular priority assignment period. If the mask allows for no allowable requestors during the priority assignment period, a reset-mask scheme is implemented to reset the mask to permit an increased number of requestors access to the priority arbitration scheme.

Abstract: A clock generator is provided. The clock generator includes a crystal oscillator, an inverter coupled to the crystal oscillator in parallel, a first circuit and a second circuit. The crystal oscillator has a first terminal and a second terminal. The inverter generates a first signal and a second signal at the first and second terminals of the crystal oscillator, respectively. The first circuit coupled to the first terminal of the crystal oscillator generates a first clock signal with a constant frequency according to the first signal. The second circuit coupled to the second terminal of the crystal oscillator generates a second clock signal with a variable frequency according to the second signal.

Abstract: A method, system and computer program product are provided for implementing PCI-Express memory domains for single root virtualized devices. A PCI host bridge (PHB) includes a memory mapped IO (MMIO) domain descriptor (MDD) and an MMIO Domain Table (MDT) are used to associate MMIO domains with PCI memory VF BAR spaces. One MDD is provided for each unique VF BAR space size per bus segment connecting a single root IO virtualization (SRIOV) device to the PCI host bridge (PHB). The MDT used with the MDD includes having a number of entries limited to a predefined total number of SRIOV VFs to be configured. A VF BAR Stride, which may be further implemented as a VF BAR Stride Capability Structure, is provided to reduce the number of MDDs required to map SRIOV VF BAR spaces. A particular definition of the MDD is provided to reduce the number of MDDs required to at most one per SRIOV bus segment below a PHB.

Abstract: Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a command from a first bus, the command having an identification field having a value. The command is then entered into a buffer in the bridge unless another command having the same identification field value exists in the buffer. Once the command with the same identification field value is removed from the buffer, the received command is entered into the buffer. Next, the buffered command is transmitted over a second bus. A response to the command is eventually received from the second bus, the response is transmitted over the first bus, and the command is then removed from the buffer. By not entering the received command until a similar command with the same identification value is removed from the buffer, command ordering is enforced even though multiple commands are pending in the buffer.

Abstract: An adapter for connecting an accessory to a portable electronic device includes a first connector compatible with a connector of the portable electronic device and a second connector compatible with a connector of the accessory. The connectors of the accessory and the portable electronic device are otherwise incompatible with each other. The adapter provides two levels of authentication. First, the adapter authenticates itself to the portable electronic device. If this first authentication is successful, then the adapter authenticates the accessory to the adapter.

Abstract: Provided is a method capable of providing an improved response property appropriate for the characteristics of a system by automatically choosing an interrupt handling mode used for each device. The method is a method in which the embedded operating system kernel determines a handling mode for all individual interrupts, the method includes: dividing interrupt handling modes into a first interrupt handling mode and a second interrupt handling mode which has a different process speed from the first interrupt handling mode, and variably determining a distribution ratio in which each of the interrupts are distributed to the first interrupt handling mode or to the second interrupt handling mode according to a predetermined process condition during boot-up.