Abstract: Handshaking circuits are provided in a communications cable and in a device operable to be mated with the communications cable. Before a device can utilize the power supply signal of such a communications channel, the two handshaking circuits must sufficiently identify one another over a power supply signal with a decreased voltage. The decreased voltage allows for a cable plug to be provided with a safe, protected power that cannot cause harm to a human. The decreased voltage also reduces the chance that a device can receive a primary power supply signal from the cable before the device sufficiently identifies itself. Accordingly, a laptop may be connected to a portable music player, but the voltage of the power supply signal provided by the laptop to the cable may be decreased on-cable until the handshaking circuit of the portable music player sufficiently performs a handshaking operation with a on-cable handshaking circuit.

Abstract: A load management method and system. The method includes detecting and monitoring by a computing system, a frequency signal associated with an input voltage signal used for powering computing apparatuses at a specified location. The computing system compares the frequency signal to a predetermined frequency value. The computing system determines that the frequency signal comprises a first value that is not equal to the predetermined frequency value. The computing system calculates a difference value between the first value and the predetermined frequency value. The computing system compares the difference value to a second value and analyzes a power demand profile. The computing system enables a load adjustment modification process associated with the plurality of power consumption devices based on the difference value and the power demand profile. The computing system generates and stores a report associated with the load adjustment modification process.

Abstract: A bridge includes a host interface via which data/commands are received from and transferred to a host, and a storage device interface via which data/commands are received from and transferred to a storage device. The bridge also includes one SDPC, a controller and a switching system that is configurable by the controller to connect the protocol converter to the host interface and the storage device interface if the storage device protocol used by the host device differs from the storage device protocol used by the storage device, and to connect the host device interface to the storage device interface, not via the bi-directional protocol converter, if the two storage device protocols are the same. The bridge may include two SDPCs, each for converting a different protocol to the host protocol and vice versa, with the switching system being configurable to switch between the two SDPCs.

Abstract: A legacy adapter for use with devices to be powered by a power adapter is described. The legacy adapter includes a multi-purpose power connector configured to couple to a power adapter external to the electrical device, a connector configured to connect the electrical device, and a microprocessor configured to communicate digitally with the power adapter. The microprocessor communicates power requirements of the electrical device to the power adapter through the multi-purpose power connector. A related method of receiving power from a power adapter external to an electrical device through a legacy adapter is also described.

Abstract: Provided is a digital image transmission system in a high definition multimedia interface (HDMI) format or a digital visual interface (DVI) format. A transmission and reception reinforcement device of the digital image transmission system includes a transmitter, a receiver, and a power supply circuit. The power supply circuit includes a first power supply unit supplying power to the transmitter and a second power supply unit supplying power to the receiver. Power output terminals of the first and second power supply units are connected to each other. External-power supply voltages respectively input to the first and second power supply units are output to the power output terminals. When all of the external-power supply voltages input to the first and second power supply units are lower than a predetermined voltage, an internal-power supply voltage present in a communication line between the host device and the display device is output to the power output terminals.

Abstract: This disclosure describes a processor system that allows non-real time code to execute normally, while permitting a real time interrupt in hardware or software to execute with minimal added latency.

Abstract: Systems and methods for optimizing the power of a battery in a mobile device are provided. The systems and methods include receiving a request from at least one of a plurality of applications running on the mobile device. The systems and methods further include determining user characteristics from interacting with at least one of the applications and determining a user dwell time threshold based upon the user's interactions with an application. The systems and methods further include buffering requests if the user dwell time is less than the user dwell threshold level.

Abstract: Dissipating power from a power supply. At least some of the illustrative embodiments are motherboards including a printed circuit board configured to couple to a main processor (and the printed circuit board configured to couple to a main power signal and an auxiliary power signal of a power supply), and a power dissipation circuit on the printed circuit board. The power dissipation circuit is configured to detect that the main power signal has powered-off, and responsive to the detection dissipate power from the auxiliary power signal for a predetermined amount of time less than an amount of time needed to fully discharge the auxiliary power signal in the absence of alternating current (AC) power to the power supply.

Abstract: Efficient techniques are described for identifying active interrupt requests to improve performance and reduce power requirements in a processor system. A method to identify active sampled interrupt requests begins with scanning groups of the sampled interrupt requests one group at a time to identify an active interrupt request in any scanned group. A group of interrupt requests is an M/R priority of N sampled interrupt requests, M is the number of priority levels, and R is a resource sharing factor. A group selection circuit is updated to a new group in response to having identified an active interrupt request to improve the latency in processing high priority interrupt requests. Also, groups having active interrupt requests may be identified by early detection or look ahead circuitry. The scanning of groups of interrupt requests may be stopped until the next interrupt request sample point has been reached to reduce power utilization.

Abstract: A signal transmission system includes a transmitting device and a receiving device. The transmitting device includes a superimposition portion that superimposes at least one synchronizing signal on at least one video signal among a plurality of video signals, and outputs the synchronizing signal and the video signal as a superimposition signal to a receiving device. The receiving device includes a separation portion that separates the superimposition signal into the synchronizing signal and the video signal, a first adjustment portion that adjusts an amount of delay of the separated video signal to another video signal, and a second adjustment portion that adjusts an amount of delay of the separated synchronizing signal.

Abstract: A multi-core bus termination apparatus includes a location array and a plurality of drivers. The location array generates a plurality of location signals that indicate locations on the bus of a corresponding plurality of nodes that are coupled to the bus, where the locations comprise either an internal location or a bus end location. Each of the plurality of drivers has one of the corresponding plurality of nodes, and controls how the one of the corresponding plurality of nodes is driven responsive to a state of a corresponding one of the plurality of location signals. Each of the plurality of drivers has configurable multi-core logic. The configurable multi-core logic enables pull-up logic and first pull-down logic if the state indicates the bus end location. The configurable multi-core logic disables the pull-up logic and to enable the first pull-down logic and second pull-down logic if the state indicates the internal location.

Abstract: In one embodiment, an interrupt acceptance control circuit is provided. The interrupt acceptance control circuit may monitor one or more guest interrupt controllers in a system in response to an IPI (or device interrupt) issued in a guest, to determine if each targeted vCPU in the guest has accepted the interrupt. If not, the interrupt acceptance control circuit may communicate the lack of acceptance to the VMM, in one embodiment. The VMM may attempt to schedule the vCPUs that have not accepted the interrupt, for example.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

Abstract: A server system comprises a plurality of servers, and a management unit. Each of the servers has virtual machines which can move among the servers. The management unit moves all the virtual machines on one server to another server(s) based on information showing an electric power value so as to reduce the number of servers in operation as much as possible. The management unit stops supplying the electric power to the server on which no virtual machine has run as a result of the movement of the virtual machines.

Abstract: The present invention includes a plurality of disk units for storing data from a host computer, a plurality of power supply apparatuses for supplying DC power to each of the disk units via main power supply wirings, and a redundant power supply apparatus for generating, with any one of the disk units among the plurality of disk units as a load, DC power to the load. As auxiliary power supply wirings for guiding the output of the redundant power supply apparatus to each of the disk units, a common power supply wiring that is common to each of the power supply apparatuses, a plurality of branch power supply wirings branching from the common power supply wiring and connected to each of the disk units, and a redundant power supply wiring for connecting the redundant power supply apparatus and the common power supply wiring are wired to a backboard.

Abstract: A microprocessor that performs adaptive power throttling includes a calculation unit configured to calculate an average power consumed by the microprocessor over a most recent predetermined sample time and to determine whether the average power is less than a predetermined maximum power value. A power management unit controls the microprocessor to conditionally operate at a predetermined frequency if the average power is less than the predetermined maximum power value. The predetermined frequency is a frequency at which the microprocessor may consume more than the predetermined maximum power value. The power management unit controls the microprocessor to operate at the predetermined frequency only if the microprocessor was most recently instructed by system software to operate at a highest frequency instructable by the system software. The highest frequency instructable by the system software is less than the predetermined frequency.

Abstract: An aspect of the embodiment utilizes a selection circuit that includes a first storage circuit for storing information of m×n bits each corresponding to a choice. The storage circuit indicates whether the corresponding choice is in a selectable state or not. A first round robin circuit for executing a round robin process on the second storage circuit selects one of the bits contained in the corresponding bit string and indicates that a choice is in a selectable state. A second round robin circuit executes the round robin process on the bit string having the m-bit width to select one of the bits indicating that the corresponding choice, and a control circuit controls the first and the second round robin circuit.

Abstract: The memory module includes a plurality of memory devices, a first connector and a second connector. The first connector is disposed at a first position on the memory module. The first connector is configured to carry low-speed signals for the memory devices. The second connector is disposed at a second position on the memory module, different from the first position. The second connector is configured to carry high-speed signals for at least one of the memory devices. The high-speed signals are a higher speed form of signaling than the low-speed signals. The memory system may include at least one slot electrically connected to a chip set and at least one memory module electrically connected to the slot via the first connector. A transmission line such as a fiber optic cable electrically connects the second connector and the chip set.

Abstract: A plurality of system controllers 300 each comprising a memory medium 400 and an I/O device 500 under the control of the system controller 300 are connected to a CPU node 100 by way of a plurality of system buses 200. The CPU node 100 executes a memory interleave for distributing memory accesses to the system buses 200 (i.e., the system controllers 300). In performing an I/O access to the I/O device 500, the CPU node 100 firstly inquires from a representative system controller 300 (SC0) as to which system bus 200 (i.e., a system controller 300) has a target I/O device 500 and then executes an actual I/O access to the system bus 200 returned in a response from the SC0. Even when the CPU node 100 executes a memory interleave in the case of a memory-mapped I/O, the CPU node 100 is not required to manage the location information of the I/O device 500.

Abstract: A processing device comprises an interface and its control circuit for performing data transfer in synchronization with an external clock, an internal oscillator, and an interface and its control circuit for performing data transfer by using an internal clock generated by the internal oscillator. In the processing device, a clock control circuit that switches a system clock between the internal clock and the external clock in accordance with the interface is provided. When the system clock is switched, the switching is performed after the CPU is set in a sleep state, and after the switching is completed, the sleep state of the CPU is released to restart the operation.