Patents Examined by Matthew E. Warren
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Patent number: 11978800Abstract: An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.Type: GrantFiled: September 26, 2022Date of Patent: May 7, 2024Assignee: Acorn Semi, LLCInventors: Paul A. Clifton, R. Stockton Gaines
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Patent number: 11980035Abstract: A semiconductor device includes a first conductor structure extending along a lateral direction. The semiconductor device includes a first memory film that extends along a vertical direction and is in contact with the first conductor structure. The semiconductor device includes a first semiconductor film that extends along the vertical direction and is in contact with the first memory film. Ends of the first semiconductor film align with ends of the first memory film, respectively. The semiconductor device includes a second conductor structure extending along the vertical direction. The semiconductor device includes a third conductor structure extending along the vertical direction. The semiconductor device includes a fourth conductor structure extending along the vertical direction. The second and fourth conductor structures are coupled to the ends of the first semiconductor film, and the third conductor structure is coupled to a portion of the first semiconductor film between its ends.Type: GrantFiled: August 27, 2021Date of Patent: May 7, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Han Lin, Chia-En Huang
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Patent number: 11972342Abstract: A image sensor includes a first integrated circuit layer including pixel sensors that are grouped based on position into pixel sensor groups, a second integrated circuit layer in electrical communication with the first integrated circuit layer, the second integrated circuit layer including image processing circuitry groups that are configured to each receive pixel information from a corresponding pixel sensor group, the image processing circuitry groups further configured to perform image processing operations on the pixel information to provide processed pixel information during operation of the image sensor, a third integrated circuit layer in electrical communication with the second integrated circuit layer, and the third integrated circuit layer including neural network circuitry groups that are configured to each receive the processed pixel information from a corresponding image processing circuitry group and perform analysis for object detection on the processed pixel information during operation of theType: GrantFiled: June 14, 2021Date of Patent: April 30, 2024Assignee: Waymo LLCInventors: Lucian Ion, Vlad Constantin Cardei, Carl Warren Craddock
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Patent number: 11974441Abstract: A 3D memory array in which epitaxial source/drain regions which are horizontally merged and vertically unmerged are used as source lines and bit lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a first channel region over a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly over the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.Type: GrantFiled: December 30, 2020Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chih-Yu Chang, Chi On Chui, Yu-Ming Lin
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Patent number: 11967610Abstract: A semiconductor device comprises a semiconductor die and an integrated capacitor formed over the semiconductor die. The integrated capacitor is configured to receive a high voltage signal. A transimpedance amplifier is formed in the semiconductor die. An avalanche photodiode is disposed over or adjacent to the semiconductor die. The integrated capacitor is coupled between the avalanche photodiode and a ground node. A resistor is coupled between a high voltage input and the avalanche photodiode. The resistor is an integrated passive device (IPD) formed over the semiconductor die. A first terminal of the integrated capacitor is coupled to a ground voltage node. A second terminal of the integrated capacitor is coupled to a voltage greater than 20 volts. The integrated capacitor comprises a plurality of interdigitated fingers in one embodiment. In another embodiment, the integrated capacitor comprises a plurality of vertically aligned plates.Type: GrantFiled: April 13, 2022Date of Patent: April 23, 2024Assignee: Semtech CorporationInventor: Christopher David Ainsworth
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Patent number: 11967627Abstract: A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, and a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, and in the cell portion, formed to be thinner than a part in the outer peripheral portion.Type: GrantFiled: July 13, 2022Date of Patent: April 23, 2024Assignee: ROHM CO, LTD.Inventors: Yuki Nakano, Ryota Nakamura
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Patent number: 11968838Abstract: A device includes a semiconductor substrate; a word line extending over the semiconductor substrate; a memory film extending along the word line, wherein the memory film contacts the word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; source lines extending along the memory film, wherein the memory film is between the source lines and the word line; bit lines extending along the memory film, wherein the memory film is between the bit lines and the word line; and isolation regions, wherein each isolation region is between a source line and a bit line, wherein each of the isolation regions includes an air gap and a seal extending over the air gap.Type: GrantFiled: August 30, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Chen Wang, Kai-Hsuan Lee, Sai-Hooi Yeong, Chi On Chui
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Patent number: 11968840Abstract: A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.Type: GrantFiled: November 10, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yong-Jie Wu, Yen-Chung Ho, Hui-Hsien Wei, Chia-Jung Yu, Pin-Cheng Hsu, Feng-Cheng Yang, Chung-Te Lin
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Patent number: 11968841Abstract: A ferroelectric device, for instance, a metal-ferroelectric-metal (MFM) capacitor, a ferroelectric random access memory (Fe-RAM), or a ferroelectric field effect transistor (FeFET), is provided. In one aspect, the ferroelectric device is based on hafnium zirconate (HZO). The ferroelectric device can include a first electrode and a second electrode, and a doped HZO layer, which is arranged between the first electrode and the second electrode. The doped HZO layer can include a ferroelectric layer and at least two non-zero remnant polarization charge states. The doped HZO layer can be doped with at least two different elements selected from the lanthanide series, or with a combination of at least one element selected from the lanthanide series and at least one rare earth element.Type: GrantFiled: February 7, 2022Date of Patent: April 23, 2024Assignee: IMEC vzwInventors: Mihaela Ioana Popovici, Amey Mahadev Walke, Jan Van Houdt
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Patent number: 11963365Abstract: An active device, a semiconductor device and a semiconductor chip are provided. The active device includes: a channel layer; a top source/drain electrode, disposed at a top side of the channel layer; a first bottom source/drain electrode and a second bottom source/drain electrode, disposed at a bottom side of the channel layer; a first gate structure and a second gate structure, located between the top source/drain electrode and the first bottom source/drain electrode, wherein the first gate structure comprises a non-ferroelectric dielectric layer, and the second gate structure comprises a ferroelectric layer; and a third gate structure and a fourth gate structure, located between the top source/drain electrode and the second bottom source/drain electrode, wherein the third gate structure comprises a non-ferroelectric dielectric layer, and the fourth gate structure comprises a ferroelectric layer.Type: GrantFiled: February 18, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yun-Feng Kao, Katherine H Chiang
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Patent number: 11961939Abstract: A method of manufacturing a light-emitting device, including: providing a substrate structure including a top surface; forming a precursor layer on the top surface; removing a portion of the precursor layer and a portion of the substrate from the top surface to form a base portion and a plurality of protrusions regularly arranged on the base portion; forming a buffer layer on the base portion and the plurality protrusions; and forming a III-V compound cap layer on the buffer layer; wherein one of the plurality of protrusions comprises a first portion and a second portion formed on the first portion; wherein the first portion is integrated with the base portion and has a first material which is the same as that of the base portion; and wherein the buffer layer contacts side surfaces of the plurality of protrusions and a surface of the base portion.Type: GrantFiled: June 23, 2022Date of Patent: April 16, 2024Assignee: EPISTAR CORPORATIONInventors: Peng Ren Chen, Yu-Shan Chiu, Wen-Hsiang Lin, Shih-Wei Wang, Chen Ou
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Patent number: 11950428Abstract: A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and conductive pillars. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure.Type: GrantFiled: August 9, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chen Wang, Meng-Han Lin, Sai-Hooi Yeong, Yu-Ming Lin, Han-Jong Chia
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Patent number: 11950429Abstract: The present invention relates to ferroelectric capacitors, transistors, memory device, and method of manufacturing ferroelectric devices. The ferroelectric capacitor includes a first electrode, a second electrode facing the first electrode, a ferroelectric layer between the first electrode and the second electrode, and an interfacial layer between the ferroelectric layer and the first electrode or between the ferroelectric layer and the second electrode. The ferroelectric layer includes hafnium-based oxide. The interfacial layer includes HfO2.Type: GrantFiled: October 23, 2020Date of Patent: April 2, 2024Assignees: Samsung Electronics Co., Ltd., Korea Advanced Institute of Science and TechnologyInventor: Sanghun Jeon
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Patent number: 11930643Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.Type: GrantFiled: May 21, 2021Date of Patent: March 12, 2024Assignee: Micron Technology, Inc.Inventors: Daniele Vimercati, Fatma Arzum Simsek-Ege
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Patent number: 11929394Abstract: A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.Type: GrantFiled: January 13, 2022Date of Patent: March 12, 2024Assignee: ROHM CO., LTD.Inventors: Yuki Nakano, Ryota Nakamura
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Patent number: 11925030Abstract: Various embodiments of the present application are directed towards a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory device, as well as a method for forming the MFMIS memory device. According to some embodiments of the MFMIS memory device, a first source/drain region and a second source/drain region are vertically stacked. An internal gate electrode and a semiconductor channel overlie the first source/drain region and underlie the second source/drain region. The semiconductor channel extends from the first source/drain region to the second source/drain region, and the internal gate electrode is electrically floating. A gate dielectric layer is between and borders the internal gate electrode and the semiconductor channel. A control gate electrode is on an opposite side of the internal gate electrode as the semiconductor channel and is uncovered by the second source/drain region. A ferroelectric layer is between and borders the control gate electrode and the internal gate electrode.Type: GrantFiled: November 4, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chih Lai, Chung-Te Lin
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Patent number: 11916127Abstract: Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.Type: GrantFiled: June 16, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi Yang Wei, Bi-Shen Lee, Hsin-Yu Lai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang
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Patent number: 11910616Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.Type: GrantFiled: August 9, 2022Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
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Patent number: 11910614Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.Type: GrantFiled: April 1, 2022Date of Patent: February 20, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang Sup Lee, Phil Ouk Nam, Sung Yun Lee, Chang Seok Kang
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Patent number: 11903217Abstract: An integrated chip including a semiconductor layer over a substrate. A pair of source/drains are arranged along the semiconductor layer. A first metal layer is over the substrate. A second metal layer is over the first metal layer. A ferroelectric layer is over the second metal layer. The first metal layer has a first crystal orientation and the second metal layer has a second crystal orientation different from the first crystal orientation.Type: GrantFiled: August 5, 2021Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin