Patents Examined by Matthew E. Warren
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Patent number: 11631698Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.Type: GrantFiled: October 14, 2020Date of Patent: April 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin, Chi On Chui, Han-Jong Chia, Chenchen Jacob Wang
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Patent number: 11631758Abstract: A semiconductor device includes a collector layer, a base layer, and an emitter layer that are disposed above a substrate. An emitter mesa layer is disposed on a partial region of the emitter layer. In a plan view, the base electrode is disposed in or on a region which does not overlap the emitter mesa layer. The base electrode allows base current to flow to the base layer. In the plan view, a first edge forming part of edges of the emitter mesa layer extends in a first direction, and a second edge forming part of edges of the base electrode faces the first edge. A gap between the first edge and the second edge in a terminal portion located in an end portion of the emitter mesa layer in the first direction is wider than a gap in an intermediate portion of the emitter mesa layer.Type: GrantFiled: March 5, 2020Date of Patent: April 18, 2023Assignee: Murata Manufacturing Co., Ltd.Inventors: Yasunari Umemoto, Isao Obu, Kaoru Ideno, Shigeki Koya
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Patent number: 11626481Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.Type: GrantFiled: October 11, 2021Date of Patent: April 11, 2023Assignee: Micron Technology, Inc.Inventors: Zailong Bian, Janos Fucsko
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Patent number: 11611056Abstract: A display apparatus and a method of manufacturing the same are provided. The display apparatus includes a substrate, and a plurality of display devices, an encapsulation layer, a microlens array and a protective layer which are sequentially provided on the substrate, and the microlens array includes a plurality of microlenses corresponding to the plurality of display devices, and each microlens in the microlens array comprises a multi-step structure including a plurality of steps.Type: GrantFiled: April 30, 2020Date of Patent: March 21, 2023Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Gaolei Xue, Xiandong Meng, Wei Wang, Can Wang, Xiaochuan Chen
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Patent number: 11610886Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.Type: GrantFiled: July 1, 2021Date of Patent: March 21, 2023Assignee: Bell Semiconductor, LLCInventors: Qing Liu, Prasanna Khare, Nicolas Loubet
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Patent number: 11610856Abstract: An integrated circuit package may be formed comprising an interposer with a center die and a plurality of identical integrated circuit dice positioned around the center die and attached to the interposer, wherein the center die is the switch/router for the plurality of identical integrated circuit dice. The interposer comprises a substrate, a central pattern of bond pads formed in or on the substrate for attaching the center die, and substantially identical satellite patterns formed in or on the substrate for attaching identical integrated circuit dice. The central pattern of bond pads has repeating sets of a specific geometric pattern and wherein the identical satellite patterns of bond pads are positioned to form the same geometric pattern as the specific geometric pattern of the central pattern of bond pads. Thus, substantially identical conductive routes may be formed between the center die and each of the identical integrated circuit dice.Type: GrantFiled: June 24, 2019Date of Patent: March 21, 2023Assignee: Intel CorporationInventors: Robert Sankman, Dheeraj Subbareddy, Md Altaf Hossain, Ankireddy Nalamalpu
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Patent number: 11610834Abstract: A leadframe includes a first conductive layer, a plurality of conductive pillars and a first package body. The first conductive layer has a first surface and a second surface opposite to the first surface. The plurality of conductive pillars are disposed on the first surface of the first conductive layer. The first package body is disposed on the first surface of the first conductive layer and covers the conductive pillars. The conductive pillars and the first conductive layer are integratedly formed.Type: GrantFiled: October 16, 2019Date of Patent: March 21, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: You-Lung Yen, Bernd Karl Appelt
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Patent number: 11605647Abstract: According to one embodiment, a semiconductor memory device includes a ferroelectric layer and a first semiconductor layer. The first semiconductor layer is electrically connected to a first electrode and a second electrode and includes an n-type oxide semiconductor. A third electrode is opposite the first semiconductor layer. The ferroelectric layer is between the third electrode and the first semiconductor layer. A second semiconductor layer includes at least one of a Group IV semiconductor material or a p-type oxide semiconductor material. The first semiconductor layer is between the ferroelectric layer and the second semiconductor layer.Type: GrantFiled: March 1, 2021Date of Patent: March 14, 2023Assignee: Kioxia CorporationInventors: Yusuke Tanaka, Masumi Saitoh, Kensuke Ota
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Patent number: 11594553Abstract: A ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel. Each memory element within the vertical stack of memory elements includes a crystalline ferroelectric memory material portion and an epitaxial template portion.Type: GrantFiled: January 15, 2021Date of Patent: February 28, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Adarsh Rajashekhar
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Patent number: 11587950Abstract: A memory device includes a multi-layer stack, a plurality of channel layers and a plurality of ferroelectric layers. The multi-layer stack is disposed on a substrate and includes a plurality of gate layers and a plurality of dielectric layers stacked alternately. The plurality of channel layers penetrate through the multi-layer stack and are laterally spaced apart from each other, wherein the plurality of channel layers include a first channel layer and a second channel layer, and a first electron mobility of the first channel layer is different from a second electron mobility of the second channel layer. Each of the plurality of channel layers are spaced apart from the multi-layer stack by one of the plurality of ferroelectric layers, respectively.Type: GrantFiled: April 12, 2021Date of Patent: February 21, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-I Wu, Yu-Ming Lin, Shih-Lien Linus Lu, Sai-Hooi Yeong, Bo-Feng Young
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Patent number: 11588058Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.Type: GrantFiled: May 5, 2021Date of Patent: February 21, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Shinohara
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Patent number: 11581337Abstract: A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and channel layers. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure.Type: GrantFiled: January 22, 2021Date of Patent: February 14, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chen Wang, Meng-Han Lin, Sai-Hooi Yeong, Yu-Ming Lin, Han-Jong Chia
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Patent number: 11574929Abstract: A 3D memory array has data storage structures provided at least in part by one or more vertical films that do not extend between vertically adjacent memory cells. The 3D memory array includes conductive strips and dielectric strips, alternately stacked over a substrate. The conductive strips may be laterally indented from the dielectric strips to form recesses. A data storage film may be disposed within these recesses. Any portion of the data storage film deposited outside the recesses may have been effectively removed, whereby the data storage film is essentially discontinuous from tier to tier within the 3D memory array. The data storage film within each tier may have upper and lower boundaries that are the same as those of a corresponding conductive strip. The data storage film may also be made discontinuous between horizontally adjacent memory cells.Type: GrantFiled: December 7, 2020Date of Patent: February 7, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chen Wang, Feng-Cheng Yang, Meng-Han Lin, Sai-Hooi Yeong, Yu-Ming Lin, Han-Jong Chia
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Patent number: 11569176Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising multiple encapsulating layers and multiple signal distribution structures, and a method of manufacturing thereof.Type: GrantFiled: March 21, 2017Date of Patent: January 31, 2023Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.Inventors: Yi Seul Han, Tae Yong Lee, Ji Yeon Ryu
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Patent number: 11557700Abstract: An optoelectronic semiconductor component includes a primary light source including a carrier and a semiconductor layer sequence mounted thereon and configured to generate primary light, and at least one conversion unit of at least one semiconductor material adapted to convert the primary light into at least one secondary light, wherein the semiconductor layer sequence and the converter unit are separate elements, the semiconductor layer sequence includes a plurality of pixels, the pixels are configured to be controlled electrically independently of each other, the carrier includes a plurality of control units configured to drive the pixels, all pixels of a first group are free of a conversion unit and are configured to emit the primary light, all pixels of a second group of pixels include exactly one conversion unit each and are configured to emit the at least one secondary light.Type: GrantFiled: March 19, 2021Date of Patent: January 17, 2023Assignee: OSRAM OLED GmbHInventors: Isabel Otto, Alexander F. Pfeuffer, Britta Göötz, Norwin von Malm
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Patent number: 11545369Abstract: An electronic component includes a lead frame; a semiconductor chip arranged above the lead frame; and a connection layer sequence arranged between the lead frame and the semiconductor chip, wherein the connection layer sequence includes a first intermetallic layer including gold and indium or gold, indium and tin, a second intermetallic layer including indium and a titanium compound, indium and nickel, indium and platinum or indium and titanium, and a third intermetallic layer including indium and gold.Type: GrantFiled: June 29, 2021Date of Patent: January 3, 2023Assignee: OSRAM OLED GmbHInventors: Mathias Wendt, Andreas Weimar
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Patent number: 11545506Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.Type: GrantFiled: November 13, 2020Date of Patent: January 3, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Bhagwati Prasad, Joyeeta Nag, Seung-Yeul Yang, Adarsh Rajashekhar, Raghuveer S. Makala
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Patent number: 11532641Abstract: A semiconductor device includes: a stack structure including conductive patterns and insulating layers, which are alternately stacked; a channel structure penetrating the stack structure; and a memory layer penetrating the stack structure, the memory layer being disposed between the channel structure and the stack structure. The memory layer includes memory parts and dummy parts, which are alternately arranged. Each of the memory parts includes a first part between the insulating layers and a second part between the dummy parts. The first part of the memory parts have ferroelectricity.Type: GrantFiled: September 21, 2020Date of Patent: December 20, 2022Assignee: SK hynix Inc.Inventor: In Ku Kang
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Patent number: 11532343Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.Type: GrantFiled: October 6, 2020Date of Patent: December 20, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chao-I Wu, Sheng-Chen Wang, Yu-Ming Lin
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Patent number: 11532634Abstract: A nonvolatile memory device comprises a first semiconductor layer including, an upper substrate, and a memory cell array in which a plurality of word lines on the upper substrate extend in a first direction and a plurality of bit lines extend in a second direction. The nonvolatile memory device comprises a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions, the second semiconductor layer including, a lower substrate, and a substrate control circuit on the lower substrate and configured to output a bias voltage to the upper substrate. The second semiconductor layer is divided into first through fourth regions, each of the first through fourth regions having an identical area, and the substrate control circuit overlaps at least a portion of the first through fourth regions in the third direction.Type: GrantFiled: July 16, 2018Date of Patent: December 20, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-won Shim, Bong-soon Lim