Abstract: An organic light emitting device and a display apparatus are disclosed. The organic light emitting device includes an array substrate and a package substrate (2); on a side of the package substrate (2) facing the array substrate, there is provided a protrusion (7) formed of a first transparent material, a surface of the protrusion (7) is also covered with a transparent layer (8) formed of a second transparent material, and the refractive index of the second transparent material is larger than the refractive index of the first transparent material.

Abstract: An organic light-emitting device includes a substrate, an anode on the substrate, a hole transport region on the anode, an emission layer on the hole transport region, an electron transport region on the emission layer, and a cathode on the electron transport region, wherein the electron transport region includes an electron injection layer including a first material including at least one of a halide of an alkali metal, and a second material including at least one of a lanthanide metal and a alkaline earth metal, and wherein the cathode contacts the electron injection layer and includes a first metal including at least one of silver, gold, platinum, copper, manganese, titanium, cobalt, nickel, and tungsten, and a second metal including at least one of a lanthanide metal and an alkaline earth metal, wherein an amount of the first metal is equal to or greater than that of the second metal.

Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.

Abstract: Provided is a display device, including: a plurality of gate lines extending in a first direction; a plurality of source lines extending in a second direction; a gate driver configured to output a gate signal; and a plurality of gate lead-out lines extending in the second direction and being configured to transmit the gate signal to the plurality of gate lines, in which each of the plurality of gate lines is electrically connected to at least one of the plurality of gate lead-out lines, and at least one of the plurality of gate lines is electrically connected to at least two of the plurality of gate lead-out lines.

Abstract: Interconnect structures and methods for forming an interconnect structure. A sacrificial layer is formed on a substrate and an interconnect opening is formed that extends vertically through the sacrificial layer into the substrate. The interconnect opening is filled with a conductor to form a conductive feature. After filling the interconnect opening with the conductor, a dielectric layer is formed on the sacrificial layer. After the dielectric layer is formed on the sacrificial layer, the sacrificial layer is removed to form an air gap layer arranged vertically between the dielectric layer and the substrate.

Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

Abstract: The disclosure provides a display panel and a method for manufacturing the same. The display panel includes: an underlying substrate; thin film transistors, a light emission layer, a first inorganic moisture-blocking layer successively arranged on the underlying substrate; an organic buffer layer arranged on the first inorganic moisture-blocking layer, the organic buffer layer comprises: droplet micro-structures for decentralizing a stress on the organic buffer layer; a second inorganic moisture-blocking layer arranged on the organic buffer layer; and a blocking layer, and a glass cover plate successively arranged on the second inorganic moisture-blocking layer.

Abstract: The present disclosure provides an organic light-emitting pixel with four subpixels formed in two groups, each group having two adjacent subpixels. The organic light-emitting pixel includes a first electrode layer formed on a substrate, including a plurality of first electrodes, each first electrode corresponding to one of the subpixels; a second electrode layer; and a first functional layer corresponding to three of the four subpixels. The first function layer is configured to adjust a distance between a first electrode and the second electrode layer. The organic light-emitting pixel also includes a light-emitting layer including a first portion and a second portion, the first portion corresponding to one of the two groups of subpixels and the second portion corresponding to another one of the two groups of subpixels, respectively.

Abstract: An image sensor includes a plurality of photodiodes disposed in a semiconductor material and a plurality of isolation structures disposed between individual photodiodes in the plurality of photodiodes. The plurality of isolation structures electrically isolate individual photodiodes in the plurality of photodiodes. A plurality of transistors are disposed proximate to the plurality of photodiodes and include a reset transistor, an amplifier transistor, and a row select transistor. An active region and a gate electrode of at least one transistor in the plurality of transistors are vertically aligned with an isolation structure in the plurality of isolation structures.

Abstract: An organic light-emitting diode (OLED) display device and an OLED display apparatus using the same are disclosed. The OLED display device includes a plurality of pixels (16) arranged in an array on a substrate (11), a side surface of a light-emitting layer (13) of the pixels (16) being covered with a first insulating structure (14) having a refractive index less than that of the light-emitting layer (13). The OLED display device has a high light extracting rate.

Abstract: A reconfigurable phase change device with methods for operating and forming the same are disclosed. An example device can comprise a reconfigurable layer comprising a phase change material, and a set of contacts connected with the reconfigurable layer. The set of contacts can comprise at least a first contact, a second contact, and a third contact. The device can comprise at least one control element electrically coupled with one or more of the set of contacts. The at least one control element can be configured to supply a first control signal to one or more of the set of contacts. The first control signal can be configured to modify a first portion of the reconfigurable layer thereby isolating the first contact from the second contact and the third contact.

Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, an interlayer dielectric, an inter-source layer, an inter-source plug, an inter-drain layer, an inter-drain plug, an inter-gate layer, and an inter-gate plug. The active layer is made of III-V group semiconductors. The source electrode, the drain electrode, and the gate electrode are disposed on the active layer. The gate electrode is disposed between the source electrode and the drain electrode. The interlayer dielectric covers the source electrode, the drain electrode, and the gate electrode. The inter-source layer, the inter-drain layer, and the inter-gate layer are disposed on the interlayer dielectric. The inter-source plug is electrically connected to the source electrode and the inter-source layer. The inter-drain plug is electrically connected to the drain electrode and the inter-drain layer. The inter-gate plug is electrically connected to the gate electrode and the inter-gate layer.

Abstract: A TFT array substrate, OLED display including the same, and a manufacturing method of the OLED display are disclosed. In one aspect, the TFT array substrate includes a substrate and a TFT formed over the substrate. The TFT includes an active layer, a gate electrode, a source electrode, a drain electrode, a first insulating layer interposed between the gate electrode and the source and drain electrodes. Each of the source and drain electrodes is interposed between the active layer and the first insulating layer. The TFT array substrate also includes a capacitor formed over the substrate and having lower and upper electrodes and a pixel electrode electrically connected to the TFT.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including an active fin protruding from a substrate and extending in a first direction, a first device isolation region disposed at a sidewall of the active fin and extending in a second direction, the second direction crossing the first direction, a normal gate electrode crossing the active fin, a first dummy gate electrode having an undercut portion on the first device isolation region, the first dummy gate electrode extending in the second direction, and a first filler filling the undercut portion on the first device isolation region, wherein the undercut portion is disposed at a lower portion of the first dummy gate electrode.

Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N?2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.

Abstract: A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.

Abstract: A semiconductor device and method of manufacturing same are described. A first hafnium oxide (HfO2) layer is formed on a substrate. A titanium (Ti) layer is formed over the first hafnium oxide layer. A second hafnium oxide layer is formed over the titanium layer. The composite device structure is thermally annealed to produce a high-k dielectric structure having a hafnium titanium oxide (HfxTi1-xO2) layer interposed between the first hafnium oxide layer and the second hafnium oxide layer.

Abstract: A semiconductor structure can include a substrate, a high-voltage blocking layer overlying the substrate, a doped buffer layer overlying the high-voltage layer, and a channel layer overlying the doped buffer layer, wherein the doped buffer layer and the channel layer include a same compound semiconductor material, and the doped buffer layer has a carrier impurity type at a first carrier impurity concentration, the channel buffer layer has the carrier impurity type at a second carrier impurity concentration that is less than the first carrier impurity concentration. In an embodiment, the channel layer has a thickness of at least 650 nm. In another embodiment, the high-voltage blocking includes a proximal region that is 1000 nm thick and adjacent to the doped buffer layer, and each of the proximal region, the doped buffer layer, and the channel layer has an Fe impurity concentration less than 5×1015 atoms/cm3.

Abstract: An electronic device comprising a bidirectional JFET can include a drain/source region; a lightly doped semiconductor layer overlying the drain/source region; a source/drain region overlying the lightly doped semiconductor layer; a trench extending through the source/drain region and into the lightly doped semiconductor layer; a gate electrode of the bidirectional JFET within the trench; and a field electrode within the trench. A process of forming an electronic device can include providing a workpiece including a first doped region and a lightly doped semiconductor layer overlying the first doped region; defining a trench extending into the lightly doped semiconductor layer; forming a gate electrode within the trench, wherein the gate electrode extends to a sidewall of the trench; and forming a field electrode within the trench, wherein a bidirectional JFET includes the first doped region, the lightly doped semiconductor layer, a second doped region, and the gate electrode.

Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.