Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a plurality of gates disposed above the quantum well stack, wherein at least two of the gates are spaced apart in a first dimension above the quantum well stack, at least two of the gates are spaced apart in a second dimension above the quantum well stack, and the first and second dimensions are perpendicular; and an insulating material disposed above the quantum well stack, wherein the insulating material extends between at least two of the gates spaced apart in the first dimension, and the insulating material extends between at least two of the gates spaced apart in the second dimension.

Abstract: Embodiments are provided to simulate a quantum circuit. A system receives a quantum circuit (or its representation), generates a graph, and adds edges for each n-qubit of fusion to be applied. Costs are estimated or calculated for various paths of gate fusion between endpoints in the graph. One or more paths are selected, for example, the lowest cost path based on a Dijkstra algorithm evaluation. A unitary matrix for each gate fusion is then generated for simulating the quantum circuit. A simulation is performed locally or remotely based on the gate fusions along the selected one or more paths, and thus, improving the memory and processor performance of the simulation.

Abstract: In a piezoelectric element, shift of a resonance point to a low-pitched sound side is achieved. A resonance point of a piezoelectric element moves to a low-pitched sound side when an active region is configured to be surrounded by an inactive region as in the configuration of the piezoelectric element. According to the piezoelectric element whose resonance point is moved to a low-pitched sound side, the piezoelectric element can realize a sound pressure that is sufficiently high for practical use when it is applied to an acoustic device.

Abstract: Disclosed is a method of facilitating straining of a semiconductor element (331) for semiconductor fabrication. In a described embodiment, the method comprises: providing a base layer (320) with the semiconductor element (331) arranged on a first base portion (321) of the base layer (320), the semiconductor element (331) being subjected to a strain relating to a characteristic of the first base portion (321); and adjusting the characteristic of the first base portion (321) to facilitate straining of the semiconductor element (331).

Abstract: A method and a device for preparing an inductance element, an inductance element, and a superconducting circuit are provided. The method includes acquiring a compound for preparing an inductance element, a superconducting coherence length and a magnetic field penetration depth of the compound meeting a preset condition; and annealing the compound to cause decomposition between a non-superconductor phase and a superconductor phase in the compound to generate the inductance element, the kinetic inductance of the inductance element being greater than the geometric inductance of the inductance element.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a first piezoelectric layer, and a first dummy layer. The first piezoelectric layer is over the substrate, and the first piezoelectric layer has a first top surface. The first dummy layer is over the first piezoelectric layer, and the first dummy layer has a second top surface. And an average roughness of the first top surface is greater than an average roughness of the second top surface. A method for manufacturing the semiconductor structure is also provided.

Abstract: Structures including a photodetector and methods of fabricating such structures. The photodetector is positioned over the top surface of the substrate. The photodetector includes a portion of a semiconductor layer comprised of a semiconductor alloy, a p-type doped region in the portion of the semiconductor layer, and an n-type doped region in the portion of the semiconductor layer. The p-type doped region and the n-type doped region converge along a p-n junction. The portion of the semiconductor layer has a first side and a second side opposite from the first side. The semiconductor alloy has a composition that is laterally graded from the first side to the second side of the portion of the semiconductor layer.

Abstract: Semiconductor devices includes third arms. A channel from the first and second arms extends to a channel of the third arm. When a current from a first voltage is flowing from the first arm to the second arm, a flow of ballistic electrons is generated that flow through the third arm channel from the channel of the first and second arms to the third arm channel. A fin structure located in the third arm channel and includes a gate. The gate is controlled using a second voltage over the fin structure, the fin structure is formed to induce an energy-field structure that shifts by an amount of the second voltage to control an opening of the gate that the flow of ballistic electrons pass through, which in turn changes a depletion width, subjecting the ballistic electrons to diffraction, and then interference.

Abstract: A superconducting circuit includes a Josephson junction device including a lower superconducting material layer formed on a substrate and a junction layer formed on the lower superconducting material layer. The superconducting circuit also includes an upper superconducting material layer formed over the junction layer. At least the lower superconducting material layer comprises grains having a size that is larger than a size of the Josephson junction.

Abstract: A method of fabricating a superconducting-semiconducting stack includes cleaning a surface of a substrate, the substrate comprising a group IV element; depositing an insulating buffer layer onto the substrate, the insulating buffer layer comprising the group IV element; depositing a p-doped layer onto the insulating buffer layer; depositing a diffusion barrier onto the p-doped layer; and processing the superconducting-semiconducting stack through dopant activation.

Abstract: A memory system comprising a qubit array configured to store therein one or more entangled qubit states encoded using a quantum stabilizer code. The memory system further comprises a quantum-state-refresh module configured to refresh an entangled qubit state in the qubit array when a degradation error is detected therein. The quantum-state-refresh module is further configured to detect the degradation error by performing a redundant measurement of a set of syndrome values corresponding to the quantum stabilizer code. The redundant measurement is based on an error-correction code defined using the generator matrix of the quantum stabilizer code and a corresponding supplemental parity-check matrix. In an example embodiment, each of the generator and supplemental parity-check matrices has a respective inclined-stripe form.

Abstract: A method of fabricating a memory device includes forming an oxide layer on a semiconductor substrate, and forming an isolation structure in the semiconductor substrate and the oxide layer to define an active area. The method also includes forming a word line and a bit line in the semiconductor substrate, wherein the bit line is above the word line. The method further includes removing the oxide layer to form a recess between the isolation structure and the bit line, and forming a storage node contact in the recess. In addition, from a top view, the storage node contact of the memory device overlaps a corresponding portion of the active area.

Abstract: Techniques regarding qubit structures comprising ion implanted Josephson junctions are provided. For example, one or more embodiments described herein can comprise an apparatus that can include a strip of superconducting material coupling a first superconducting electrode and a second superconducting electrode. The strip of superconducting material can have a first region comprising an ion implant and a second region that is free from the ion implant.

Abstract: A quantum circuit generator for a quantum computer includes a controller; and a plurality of analog conversion units (ACUs) operatively connected to the controller, each ACU being operatively connected to a corresponding qubit of a plurality of qubits, wherein each ACU is configured to convert a digital input from the controller into an analog input at a microwave frequency to control a quantum state of the corresponding qubit. The controller is configured to generate a quantum circuit using at least two qubits of the plurality of qubits, the at least two qubits being selected by the controller based on corresponding classical bits being mapped by the controller and based on latency of the generated quantum circuit so that the generated quantum circuit has a latency less than a threshold latency.

Abstract: A hybrid quantum system performs high-fidelity quantum state transduction between a superconducting (SC) microwave qubit and the ground state spin system of a solid-state artificial atom. This transduction is mediated via an acoustic bus connected by piezoelectric transducers to the SC microwave qubit. For SC circuit qubits and diamond silicon vacancy centers in an optimized phononic cavity, the system can achieve quantum state transduction with fidelity exceeding 99% at a MHz-scale bandwidth. By combining the complementary strengths of SC circuit quantum computing and artificial atoms, the hybrid quantum system provides high-fidelity qubit gates with long-lived quantum memory, high-fidelity measurement, large qubit number, reconfigurable qubit connectivity, and high-fidelity state and gate teleportation through optical quantum networks.

Abstract: Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 ?A/?m2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.

Abstract: An electronic device (e.g., a diode) is provided that includes a substrate and a patterned layer of superconducting material disposed over the substrate. The patterned layer forms a first electrode, a second electrode, and a loop coupling the first electrode with the second electrode by a first channel and a second channel. The first channel and the second channel have different minimum widths. For a range of current magnitudes, when a magnetic field is applied to the patterned layer of superconducting material, the conductance from the first electrode to the second electrode is greater than the conductance from the second electrode to the first electrode.

Abstract: A method of fabricating a superconductor device includes providing a first metal layer on top of the substrate. An oxidation of a top surface of the first metal layer is rejected. A second metal layer is deposited on top of the second metal layer. A superconducting alloy of the first metal layer and the second metal layer is created between the first metal layer and the second metal layer. There is no oxide layer between the superconducting alloy and the first metal layer.

Abstract: Josephson junction (JJ) structures are disclosed. In some embodiments, a JJ structure may include a first superconducting structure and a second superconducting structure disposed on a plane parallel to a silicon wafer surface. A non-superconducting structure may be disposed between the first superconducting structure and the second superconducting structure. A direction of current flow through the non-superconducting structure may be parallel to the silicon wafer surface.

Abstract: A method for forming a MEMS device is provided. The method includes forming a stack of piezoelectric films and metal films on a base layer, wherein the piezoelectric films and the metal films are arranged in an alternating manner. The method also includes forming a first trench in the stack of the piezoelectric films and the metal films. The method further includes forming at least one void at the side wall of the first trench. In addition, the method includes forming a spacer structure in the at least one void. The method further includes forming a contact in the first trench after the formation of the spacer structure.