Abstract: A method for generating a random number for use in a stochastic rounding operation is provided. The method includes executing an instruction that causes at least two operands to produce an intermediate result and incrementing a state of a random number generator. The method d further includes causing the random number generator to generate a random number in accordance with the state and producing a final result by utilizing the random number to determine a rounding of the intermediate result.

Abstract: A method and computer system are provided for performing a comparison computation, e.g. for use in a check procedure for a reciprocal square root operation. The comparison computation compares a multiplication of three values with a predetermined value. The computer system performs the multiplication using multiplier logic which is configured to perform multiply operations in which two values are multiplied together. A first and second of the three values are multiplied to determine a first intermediate result, w1. The digits of w1 are separated into two portions, w1,1 and w1,2. The third of the three values is multiplied with w1,2 and the result is added into a multiplication of the third of the three values with w1,1 to thereby determine the result of multiplying the three values together. In this way the comparison is performed with high accuracy, while keeping the area and power consumption of the multiplier logic low.

Abstract: According to some embodiments, a system comprises a generator of a truly random signal is connected to an input and feedback device for the purpose of providing a user with real time feedback on the random signal. The user observes a representation of the signal in the process of an external physical event for the purpose of finding a correlation between the random output and what happens during the physical event. In some examples, the system is preferably designed such the system is shielded from all classically known forces such as gravity, physical pressure, motion, electromagnetic fields, humidity, etc. and/or, such classical forces are factored out of the process as much as possible. The system is thus designed to be selectively response to signals from living creatures, in particular, humans.

Abstract: A peak frequency detection device provided with: an n multiplication unit that multiplies each element of a digital data string by n (n is an integer of 2 or more); an FFT unit that derives, as a virtual peak frequency, a frequency that corresponds to the maximum value of a power spectrum that is obtained by performing a fast Fourier transform of a digital data string of N (N is an integer of a power of 2 and is determined in accordance with a sampling frequency (fs), a sampling resolution (ftg), and a time window length (Ttg)) sample frequencies (fs) that are multiplied by n; and a 1/n multiplication unit that outputs the value of the virtual peak frequency multiplied by 1/n as the peak frequency of the digital data string. The peak frequency detection device satisfies n?1/(ftg×Ttg), fs/(n×ftg)?N?fs×Ttg, and fs>2×n×fch.

Abstract: An arithmetic processing method is provided using a binary fixed-point arithmetic processing circuit to carry out an operation of multiplicatively dividing a dividend by a divisor. The method comprises shifting the divisor by a specific number of bits when the absolute value of the divisor is within a specific range, and holding the divisor without shifting the divisor when the absolute value of the divisor is out of the specific range, acquiring an initial value of approximation calculation for the divisor that is shifted or held without being shifted, calculating a reciprocal of the divisor by performing asymptotic approximation of the acquired initial value more than once, and calculating a product of the calculated reciprocal and the dividend, and shifting the calculated product by the specific number of bits when the divisor is shifted.

Abstract: A random number generator includes a first circuit producing a random sequence of values, the first circuit having an adjustable input that changes the entropy of the random sequence of numbers; a second circuit receiving the random sequence of values from the first circuit and producing an output indicative of the degree of entropy of the random sequence of values, and a third circuit that adjusts the adjustable input of the first circuit in response to the output of the second circuit.

Abstract: A first calculation unit is capable of calculating f(x)bx1 and sets a calculation result of f(x)bx1 to u, and a second calculation unit is capable of calculating f(x)ax2, and sets a calculation result of f(x)ax2 to v. A final calculation unit outputs (ub?va?)1/d for d=a?a+b?b when the calculation result u and the calculation result v satisfy ua=vb. Here, G and H are groups, f is a function for mapping an element x of the group H to the group G, X1 and X2 are random variables values of which are in the group G, a realization of the random variable X1 is x1, a realization of the random variable X2 is x2, and a, b, a?, and b? are integers.

Abstract: An apparatus and method that stabilizes an output sequence of a real random number generator by adjusting the input voltage of the random number generator or the comparative voltage of a comparator. The apparatus for stabilizing an output sequence of a real random number generator includes a verification unit for performing a monobit test on random number values sampled by and output from a comparison unit, and calculating an impact value. An adjustment unit adjusts a voltage of any one of a random number generation unit and the comparison unit using resulting values of the monobit test and the impact value output from the verification unit.

Abstract: An adder for supporting multiple data types by controlling a carry propagation is provided. The adder includes a plurality of first addition areas configured to receive pieces of incoming operand data, wherein each of the plurality of first addition areas includes a predetermined unit number of bits, and a plurality of second addition areas configured to receive pieces of control data based on a type of the operand data and an operation type, wherein the plurality of second addition areas are alternately arranged between the plurality of first addition areas.

Abstract: Provided are, among other things, systems, apparatuses methods and techniques for generating discrete-time sinusoidal sequences. One such apparatus includes a plurality of parallel processing branches, with each of the parallel processing branches operating at a subsampled rate and utilizing a recursive filter to generate sub-rate samples which represent a different subsampling phase of a complete signal that is output by the apparatus.

Abstract: A method and system are disclosed for solving a convex integer quadratic programming problem using a binary optimizer, the method comprising use of a processor for receiving a convex integer quadratic programming problem; converting the convex integer quadratic programming problem into a plurality of constrained and unconstrained binary quadratic programming problems and providing the plurality of unconstrained binary quadratic programming problems to the binary optimizer to thereby solve the convex integer quadratic programming problem.

Abstract: A method of encoding data includes selecting a line to define an adjustment target coefficient group in each of a plurality of coefficient groups included in a transform unit that has been transformed and quantized. Each of the coefficient groups comprises a plurality of coefficients. For each of the coefficient groups, a sum of the coefficients for the respective coefficient group is calculated. For each of the coefficient groups, a value of one adjustment target coefficient included in the adjustment target coefficient group is adjusted according to a result of the calculation of the sum of the coefficients for the respective coefficient group.

Abstract: According to one general aspect, an apparatus may include a floating-point addition unit that includes a far path circuit, a close path circuit, and a final result selector circuit. The far path circuit may be configured to compute a far path result based upon either the addition or the subtraction of the two floating point numbers regardless of whether the operands or the result include normal or denormal numbers. The close path circuit may be configured to compute a close path result based upon the subtraction of the two floating point operands regardless of whether the operands or the result include normal or denormal numbers. The final result selector circuit may be configured to select between the far path result and the close path result based, at least in part, upon an amount of difference in the exponent portions of the two floating point operands.

Abstract: A method includes receiving a first element of a Galois Field of order qm, where q is a prime number and m is a positive integer. The first element is raised to a predetermined power so as to form a second element z, wherein the predetermined power is a function of qm and an integer p, where p is a prime number which divides qm?1. The second element z is raised to a pth power to form a third element. If the third element equals the first element, the second element multiplied by a pth root of unity raised to a respective power selected from a set of integers between 0 and p?1 is output as at least one root of the first element.

Abstract: An information processing method for system identification includes: generating a fitting curve represented by a sum of exponential functions for each of a set of digital inputs and a set of digital outputs for a physical system that is represented by one or plural equations including m-order differential operators (m is an integer equal to or greater than 1); and calculating coefficients of the differential operators, which are included in first coefficients, so that a first coefficient of each exponential function included in an expression obtained by a product of the differential operators and the fitting curve for the set of the digital inputs is equal to a second coefficient of the same exponential function, which is included in the fitting curve for the set of the digital outputs.

Abstract: A division operation apparatus is provided. The division operation apparatus includes a memory, a non-zero bit detection circuit, a mapping calculation circuit, a look-up circuit, a compensation circuit and a multiplication circuit. The memory stores a divisor look-up table including a plurality of entries. The non-zero bit detection circuit detects a number of a highest non-zero bit of the divisor. The mapping calculation circuit generates a mapped value of the divisor within a range of the divisor look-up table according to a mapping function. The look-up circuit retrieves a corresponding entry having a stored reciprocal according to the mapped value. The compensation circuit generates a compensation value according to the mapping function. The multiplication circuit multiplies a dividend, the stored reciprocal and the compensation value to generate a divided result of the dividend and the divisor.

Abstract: Disclosed herein is a shared memory systems that use a combination of SBR and MRRR techniques to calculate eigenpairs for dense matrices having very large numbers of rows and columns. The disclosed system allows for the use of a highly scalable tridiagonal eigensolver. The disclosed system likewise allows for allocating a different number of threads to each of the different computational stages of the eigensolver.

Abstract: This invention is a digital signal processor form plural sums of absolute values (SAD) in a single operation. An operational unit performing a sum of absolute value operation comprising two sets of a plurality of rows, each row producing a SAD output. Plural absolute value difference units receive corresponding packed candidate pixel data and packed reference pixel data. A row summer sums the output of the absolute value difference units in the row. The candidate pixels are offset relative to the reference pixels by one pixel for each succeeding row in a set of rows. The two sets of rows operate on opposite halves of the candidate pixels packed within an instruction specified operand. The SAD operations can be performed on differing data widths employing carry chain control in the absolute difference unit and the row summers.

Abstract: A processing apparatus has combined divide-square root circuitry for performing a radix-N SRT divide algorithm and a radix-N SRT square root algorithm, where N is an integer power-of-2. The combined circuitry has shared remainder updating circuitry which performs remainder updates for a greater number of iterations per cycle for the SRT divide algorithm than for the SRT square root algorithm. This allows reduced circuit area while avoiding the SRT square root algorithm compromising the performance of the SRT divide algorithm.

Abstract: A microprocessor splits a fused multiply-accumulate operation of the form A*B+C into first and second multiply-accumulate sub-operations to be performed by a multiplier and an adder. The first sub-operation at least multiplies A and B, and conditionally also accumulates C to the partial products of A and B to generate an unrounded nonredundant sum. The unrounded nonredundant sum is stored in memory shared by the multiplier and adder for an indefinite time period, enabling the multiplier and adder to perform other operations unrelated to the multiply-accumulate operation. The second sub-operation conditionally accumulates C to the unrounded nonredundant sum if C is not already incorporated into the value, and then generates a final rounded result.